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Chip-Level CMOS Co-Integration of ReRAM-Based Non-Volatile Memories

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Chip-Level CMOS Co-Integration of ReRAM-Based Non-Volatile Memories

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A ReRAM-Based Non-Volatile Flip-Flop with Sub-VT Read and CMOS Voltage-Compatible Write

Surface potential compact model for embedded flash devices oriented to IC memory design

Using Managed Runtime Systems to Tolerate Holes in Wearable Memories

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Numerical and Compact Modeling of Embedded Flash Memory Devices Targeted for IC Design

Surface potential compact model for embedded flash devices oriented to IC memory design

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Characterization and physical modeling of endurance in embedded non-volatile memory technology

Towards generic low-power area-efficient standard cell based memory architectures

Analytical and compact models of the ONO capacitance in embedded non-volatile flash devices

Numerical and Compact Modeling of Embedded Flash Memory Devices Targeted for IC Design

A ReRAM-Based Non-Volatile Flip-Flop with Sub-VT Read and CMOS Voltage-Compatible Write

Surface potential compact model for embedded flash devices oriented to IC memory design

Characterization and physical modeling of endurance in embedded non-volatile memory technology

Using Managed Runtime Systems to Tolerate Holes in Wearable Memories

Towards Multi-Fabric 3D Integration Architectures

Analytical and compact models of the ONO capacitance in embedded non-volatile flash devices

Surface potential compact model for embedded flash devices oriented to IC memory design

Ferroelectric Field Effect Transistor for Memory and Switch Applications

Towards generic low-power area-efficient standard cell based memory architectures