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A novel design-for-test (DFT) method that requires minor modifications to the controller in the register-transfer level (RTL) description of a circuit is presented. The control/data flow graph representation of an RTL circuit is used for analysing the test ...
As dictated by ongoing technology scaling and the advent of multi-core systems, each new generation of microprocessors and digital signal processors provides higher computing power and data throughput. However, the available bandwidth of the input/output ( ...
One of the biggest challenges that are facing the Very Large Scale Integrated Circuits (VLSI) technologies today is the significant performance gap (3× to 9×) between full custom circuits and Application Specific Integrated Circuits (ASICs) designed in the ...
The quickening pace of the MOSFET technology scaling has pushed the MOSFET dimension towards 10 nanometer channel length, where it is going to face the following fundamental and performance limiting factors: (i) electrostatic limits, (ii) source to drain t ...
This graduate textbook in computer engineering offers a modern, up-to-date look at computer aided design of VLSI circuits at the functional and logic level by addressing an interesting topic in CAD for digital circuits: design synthesis of detailed specifi ...
Today's world of electronics becomes more and more digital and therefore CMOS becomes the dominant technology. A CMOS process compared to a bipolar process offers several advantages, mainly a low power consumption which is important for portable systems po ...
This article presents a novel approach for implementing ultra-low power digital components and systems using source-coupled logic (SCL) circuit topology, operating in weak inversion (sub-threshold) regime. PMOS transistors with shorted drain-substrate cont ...
Nanometer CMOS scaling has resulted in greatly increased circuit variability, with extremely adverse consequences on design predictability and yield. A number of recent works have focused on adaptive post-fabrication tuning approaches to mitigate this prob ...
A new top-down design flow (RTL-to-GDSII) is proposed for achieving high-performance and noiseimmune designs consisting of differential logic blocks. The differential building blocks are based on the currentmode logic (CML), which offers true differentiali ...
Dynamic power management is a design methodology aiming at controlling performance and power levels of digital circuits and systems, with the goal of extending the autonomous operation time of battery-powered systems, providing graceful performance degrada ...
