High Performance Tri-gate GaN Power MOSHEMTs on Silicon Substrate

We demonstrate high-performance GaN power metal-oxide-semiconductor high electron mobility transistors (MOSHEMTs) on silicon substrate based on a nanowire tri-gate architecture. The common issue of partial removal of carriers by nanowire etching in GaN tri-gate transistors was resolved mainly by optimized tri-gate geometry, including filling factor and trench width. The tri-gate reduced the OFF-state leakage current (I-OFF) and the subthreshold slope, increased the ON/OFF ratio, and improved the breakdown voltage (V-BR) of the device. With a gate-to-drain separation (L-GD) of 5 mu m, the tri-gate MOSHEMTs exhibited V-BR of 792 V at I-OFF of 0.3 mu A/mm, along with a small specific ON-resistance (R-ON, (SP)) of 0.91 +/- 0.08 m Omega.cm(2). With L-GD of 15 mu m, hard V-BR of 1755 V at I-OFF of 45 mu A/mm with high soft V-BR of 1370 V at I-OFF = 1 mu A/mm were achieved, rendering excellent high power figure of merits (FOMs) up to 1.25 GW/cm(2). These results unveil the significant potential of nanostructured GaN transistors for future power applications.