Publication
This work reports a low power implementation of a 60Gb/s NRZ optical receiver (RX) in 14nm bulk CMOS finFET featuring a first-order digital CDR with high jitter tolerance (JTOL). The design includes a single phase-rotator (PR) with low complexity control logic suitable for high-speed applications. Multi-phase clock signals that drive data/edge slicers are created by an open loop-quadrature clock generator. The circuit, characterized in an 850nm VCSEL based optical link, recovers PRBS7 data (BER
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Tobias Kippenberg, Maxim Karpov, Martin Hubert Peter Pfeiffer, Arne Kordts, Fatemeh Alishahi, Ahmad Fallahpour