Publication

Network-on-chip using request and reply trees for low-latency processor-memory communication

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While DRAM latency has long been recognized as a major bottleneck in servers, DRAM bandwidth is emerging as an important bottleneck as server processors shift to many-core architectures to allow for sustainable throughput improvements. The rapid expansion ...

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Challenges of Memory Management on Modern NUMA Systems

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The latency of memory access times is hence non-uniform, because it depends on where the request originates and where it is destined to go. Such systems are referred to as nonuniform memory access (or NUMA). Current x86 NUMA systems are cache coherent (cal ...

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Hardware-Oriented Dynamically Adaptive Disparity Estimation Algorithm and its Real-Time Hardware

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A real-time stereo camera disparity estimation device comprises input means arranged to input measured data corresponding to rows of left and right images; a plurality of on-chip memories arranged to buffer the input measured data; a vertical rotator hardw ...

2015

Ultra-Low Power Multicore Architecture For Parallel Biomedical Signal Processing

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A multi-core architecture with ultra-low power consumption is needed for a wide variety of applications, especially in the bio-medical domain. In this patent, an ultra-low power multi-core architecture is presented: it is composed of one or more cores, sev ...

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Temperature-Aware Runtime Power Management for Chip-Multiprocessors with 3-D Stacked Cache

Giovanni De Micheli, Siang-Yun Lee

The advent of 3-D fabrication technology makes it possible to stack a large amount of last-level cache memory onto a multi-core die to reduce off-chip memory accesses and, thus, increases system performance. However, the higher power density (i.e., power d ...

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Unison Cache: A Scalable and Effective Die-Stacked DRAM Cache

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Recent research advocates large die-stacked DRAM caches in manycore servers to break the memory latency and bandwidth wall. To realize their full potential, die-stacked DRAM caches necessitate low lookup latencies, high hit rates and the efficient use of o ...

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With the end of Dennard scaling, server power has emerged as the limiting factor in the quest for more capable datacenters. Without the benefit of supply voltage scaling, it is essential to lower the energy per operation to improve server efficiency. As th ...

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Since the 1970’s, microprocessor-based digital platforms have been riding Moore’s law, allowing for doubling of density for the same area roughly every two years. However, whereas microprocessor fabrication has focused on increasing instruction execution r ...

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Design Methods and Tools for Application-Specific Predictable Networks-on-Chip

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As the complexity of applications grows with each new generation, so does the demand for computation power. To satisfy the computation demands at manageable power levels, we see a shift in the design paradigm from single processor systems to Multiprocessor ...

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3D-LIN: A Configurable Low-Latency Interconnect for Multi-Core Clusters with 3D Stacked L1 Memory

Giovanni De Micheli, Yusuf Leblebici, Luca Benini, Giulia Beanato

Shared L1 memories are of interest for tightly- coupled processor clusters in programmable accelerators as they provide a convenient shared memory abstraction while avoiding cache coherence overheads. The performance of a shared-L1 memory critically depend ...

2012

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