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Ambipolar silicon nanowire field effect transistor

Publications associées (63)

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Multiple-Independent-Gate Field-Effect Transistors for High Computational Density and Low Power Consumption

Jian Zhang

Transistors are the fundamental elements in Integrated Circuits (IC). The development of transistors significantly improves the circuit performance. Numerous technology innovations have been adopted to maintain the continuous scaling down of transistors. W ...

EPFL2016

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Nanowire Field Effect Transistors (FETs) with multiple independent gates around a silicon channel feature ultimate gate control and are regarded as promising candidates for next generation transistors. Being inherently more complex than conventional gate-a ...

Institute of Electrical and Electronics Engineers2016

A tunneling field effect transistor for light detection, including a p-type region connected to a source terminal, a n-type region connected to a drain terminal, an intrinsic region located between the p-type region and the n-type region to form a P-I junc ...

2016

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In this paper, we introduce the different modes of operation achievable with Three-Independent-Gate Field-Effect Transistors (TIGFETs) and report results on fabricated devices including: (i) the dynamic reconfiguration of the device polarity; (ii) t ...

2015

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In this paper we report the results of Monte-Carlo simulations performed on double-gate ballistic MOSFETs with a geometry such that the gates overlap only a fraction of the channel. We present a qualitative analysis of the simulation results highlighting t ...

Elsevier2015

Carrier Mobility Extraction Methodology in Junctionless and Inversion-Mode FETs

Jean-Michel Sallese, Farzan Jazaeri

In this paper, we propose a new method to extract the free carrier mobility in junctionless (JL) double-gate FETs biased in accumulation. We show that, in addition to assuming a well-defined field-dependent mobility law, using the well-known Y-function is ...

Institute of Electrical and Electronics Engineers2015

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We investigate the effect of pseudo-bilayer configurations at low operating voltages (

American Institute of Physics2015

Configurable Logic Gates Using Polarity Controlled Silicon Nanowire Gate-All-Around FETs

Giovanni De Micheli, Davide Sacchetto, Yusuf Leblebici, Pierre-Emmanuel Julien Marc Gaillardon, Jian Zhang, Michele De Marchi

This work demonstrates the first fabricated 4-transistor logic gates using polarity-configurable, gate-all- around silicon nanowire transistors. This technology enhances conventional CMOS functionality by adding the degree of free- dom of dynamic polarity ...

Institute of Electrical and Electronics Engineers2014

Top-Down Fabrication of Gate-All-Around Vertically-Stacked Silicon Nanowire FETs with Controllable Polarity

Giovanni De Micheli, Davide Sacchetto, Yusuf Leblebici, Pierre-Emmanuel Julien Marc Gaillardon, Jian Zhang, Michele De Marchi

Asthe currentMOSFET scaling trend is facing strong limitations, technologies exploiting novel degrees of freedom at physical and architecture level are promising candidates to enable the continuation of Moore's predictions. In this paper, we report on the ...

Institute of Electrical and Electronics Engineers2014

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Gate-all-around (GAA) silicon nanowires enable an unprecedented electrostatic control on the semiconductor channel that can push device performance with continuous scaling. In modern electronic circuits, the control of the threshold voltage is essential fo ...

Institute of Electrical and Electronics Engineers2014