Negative Capacitance as Performance Booster for Tunnel FETs and MOSFETs: An Experimental Study

This letter reports for the first time a full experimental study of performance boosting of tunnel FETs (TFETs) and MOSFETs by negative capacitance (NC) effect. We discuss the importance of capacitance matching between a ferroelectric NC and a device capacitance to achieve hysteretic and non-hysteretic characteristics. PZT ferroelectric capacitors are connected to the gate of three terminals TFETs and MOSFETs and partial or full matching NC conditions for amplification and stability are obtained. First, we demonstrate the characteristics of hysteretic and non-hysteretic NC-TFETs. The main performance boosting is obtained for the non-hysteretic NC-TFET, where the ON-current is increased by a factor of 500 times, transconductance is enhanced by three orders of magnitude, and the low slope region is extended. The boosting of performance is moderate in the hysteretic NC-TFET. Second, we investigate the impact of the same NC booster on MOSFETs. Subthreshold swing as steep as 4 mV/decade with a 1.5-V hysteresis is obtained on a commercial device fabricated in 28-nm CMOS technology. Moreover, we demonstrate a nonhysteretic NC-MOSFET with a full matching of capacitances and a reduced subthreshold swing down to 20 mV/decade

Negative Capacitance as Universal Digital and Analog Performance Booster for Complementary MOS Transistors

Christian Enz, Mihai Adrian Ionescu, Farzan Jazaeri, Ali Saeidi, Igor Stolichnov

Boltzmann electron energy distribution poses a fundamental limit to lowering the energy dissipation of conventional MOS devices, a minimum increase of the gate voltage, i.e. 60 mV, is required for a 10-fold increase in drain-to-source current at 300 K. Negative Capacitance (NC) in ferroelectric materials is proposed in order to address this physical limitation of CMOS technology. A polarization destabilization in ferroelectrics causes an effective negative permittivity, resulting in a differential voltage amplification and a reduced subthreshold swing when integrated into the gate stack of a transistor. The novelty and universality of this approach relate to the fact that the gate stack is not anymore a passive part of the transistor and contributes to signal amplification. In this paper, we experimentally validate NC as a universal performance booster: (i) for complementary MOSFETs, of both n- and p-type in an advanced CMOS technology node, and, (ii) for both digital and analog significant enhancements of key figures of merit for information processing (subthreshold swing, overdrive, and current efficiency factor). Accordingly, a sub-thermal swing down to 10 mV/decade together with an enhanced current efficiency factor up to 105 V-1 is obtained in both n- and p-type MOSFETs at room temperature by exploiting a PZT capacitor as the NC booster. As a result of the subthreshold swing reduction and overdrive improvement observed by NC, the required supply voltage to provide the same on-current is reduced by approximately 50%.

2019

Negative Capacitance as Universal Digital and Analog Performance Booster for Complementary MOS Transistors

Christian Enz, Mihai Adrian Ionescu, Farzan Jazaeri, Ali Saeidi, Igor Stolichnov

Boltzmann electron energy distribution poses a fundamental limit to lowering the energy dissipation of conventional MOS devices, a minimum increase of the gate voltage, i.e. 60 mV, is required for a 10-fold increase in drain-to-source current at 300 K. Negative Capacitance (NC) in ferroelectric materials is proposed in order to address this physical limitation of CMOS technology. A polarization destabilization in ferroelectrics causes an effective negative permittivity, resulting in a differential voltage amplification and a reduced subthreshold swing when integrated into the gate stack of a transistor. The novelty and universality of this approach relate to the fact that the gate stack is not anymore a passive part of the transistor and contributes to signal amplification. In this paper, we experimentally validate NC as a universal performance booster: (i) for complementary MOSFETs, of both n- and p-type in an advanced CMOS technology node, and, (ii) for both digital and analog significant enhancements of key figures of merit for information processing (subthreshold swing, overdrive, and current efficiency factor). Accordingly, a sub-thermal swing down to 10 mV/decade together with an enhanced current efficiency factor up to 105 V−1 is obtained in both n- and p-type MOSFETs at room temperature by exploiting a PZT capacitor as the NC booster. As a result of the subthreshold swing reduction and overdrive improvement observed by NC, the required supply voltage to provide the same on-current is reduced by approximately 50%.

Negative Capacitance in HfO2 Gate Stack Structures With and Without Metal Interlayer

Francesco Bellando, Matteo Cavalieri, Carlotta Gastaldi, Mihai Adrian Ionescu, Ali Saeidi, Igor Stolichnov

In this work, we experimentally explore and compare FET gate stacks with and without an inner metal plane between a linear dielectric (SiO2) and a ferroelectric layer (Si-doped HfO2) operating in the negative capacitance (NC) regime. The use of nanosecond-range pulses enables us to observe hysteresis-free NC and reconstruct the S-shaped polarization-voltage curves. The devices with the inner metal plate show a higher equivalent NC value, which offers the potential for a higher differential amplification in a NC-FET. However, such a NC region is observed over a smaller range of electric field and polarization, which leads to hysteresis. Moreover, the presence of a metal layer in between the ferroelectric and the insulator favors domain formation resulting in destabilization of the NC effect. For the gate structure where the ferroelectric and the insulator are in contact, the S-shaped polarization-voltage curve shows a better agreement with Landau-Ginzburg-Devonshire formalism for the monodomain state. The uniform polarization closely mimicking the monodomain state is possible due to the polarization imprint occurring due to the structural asymmetry. By nanometer resolution polarization mapping via off-resonance piezoelectric force microscopy (PFM), we corroborate the presence of imprint, which can intrinsically stabilize one ferroelectric state. Overall, the article provides an experimental demonstration that the absence of the inner metal plane in the gate structures stabilizes the NC regime favorable for hysteresis-free NC-FET.

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022