Multi-Tone Signaling and ADC-Based Digital Receiver for High-Speed Wireline Serial Links

The exponential growth of Internet traffic and related demands for higher communication speed pushes processor-to-processor and processor-to-memory interconnects to provide further higher data-rate. Often time, processor-to-memory interconnectsâ speed is limited by reflections due to their multi-drop bus (MDB) channel nature, and processor-to-processor interconnectsâ speed is limited by inter-symbol interference due to the slowly-decaying channel pulse response and the operating speed and/or power efficiency of the equalization circuits. For the data-rate to continue its exponential growth, more complex modulation and equalization techniques should be employed in the transmitter (TX) and receiver (RX) circuits, given the power and silicon area budget. This thesis presents a signaling scheme designed to overcome equalization challenges related to reflection-limited interfaces such as MDB interfaces. By shaping the spectrum of the transmitted signal appropriately to the channelâs frequency characteristics, the proposed signaling enables minimization of energy-loss due to reflections. While the data-rate of conventional non-return-to-zero (NRZ) signaling over MDB is limited by its first notch frequency unless power-hungry decision-feedback equalizer (DFE) is employed, the proposed signaling scheme allows overcoming such limitation by simple encoding and decoding. Analogmulti-tone (AMT) signaling with single-sideband (SSB) radio-frequency (RF)-bands for efficient bandwidth usage is proposed for lossy point-to-point interfaces. The mutually orthogonal RF sub-bands feature self-equalization throughout the propagation through the communication medium and down-conversion at the RX, without necessitating the presence of conventional equalizers. To enable communication with higher modulation order for more efficient bandwidth utilization, an analog-to-digital converter (ADC)-based discrete multi-tone (DMT) RX is designed and implemented. Thanks to the high bandwidth efficiency of approximately 5.33 bits/Hz (including the cyclic prefix of DMT symbol) using 64-level quadrature amplitude modulation (64-QAM), the implemented RX undergoes less channel attenuation as compared to its 4-level pulse amplitude modulation (PAM-4) counterpart given target communication speed through the same channel. Moreover, the inherently parallel RX architecture of DMT signaling allows the RX digital signal processing (DSP) elements to be designed in semi-custom style without stringent timing constraints. Finally, a PAM-4 RX based on ADC with fully-digital equalization is presented. With register-transfer level (RTL) modeling of the designed digital equalizer, the results demonstrate the feasibility of frequency-domain equalization of the time-domain signal using Fourier transform and its inversion. The proposed frequency-domain equalization technique removes the necessity of symbol-by-symbol feedback loop in DSP that is present in DFE, relaxing critical timing constraints in DSP synthesis.

Advanced OFDM systems for terrestrial multimedia links

Renzo Posega

Recently, there has been considerable discussion about new wireless technologies and standards able to achieve high data rates. Due to the recent advances of digital signal processing and Very Large Scale Integration (VLSI) technologies, the initial obstacles encountered for the implementation of Orthogonal Frequency Division Multiplexing (OFDM) modulation schemes, such as massive complex multiplications and high speed memory accesses, do not exist anymore. OFDM offers strong multipath protection due to the insertion of the guard interval; in particular, the OFDM-based DVB-T standard had proved to offer excellent performance for the broadcasting of multimedia streams with bitrates over ten megabits per second in difficult terrestrial propagation channels, for fixed and portable applications. Nevertheless, for mobile scenarios, improving the receiver design is not enough to achieve error-free transmission especially in presence of deep shadow and multipath fading and some modifications of the standard can be envisaged. To address long and medium range applications like live mobile wireless television production, some further modifications are required to adapt the modulated bandwidth and fully exploit channels up to 24MHz wide. For these reasons, an extended OFDM system is proposed that offers variable bandwidth, improved protection to shadow and multipath fading and enhanced robustness thanks to the insertion of deep time-interleaving coupled with a powerful turbo codes concatenated error correction scheme. The system parameters and the receiver architecture have been described in C++ and verified with extensive simulations. In particular, the study of the receiver algorithms was aimed to achieve the optimal tradeoff between performances and complexity. Moreover, the modulation/demodulation chain has been implemented in VHDL and a prototype system has been manufactured. Ongoing field trials are demonstrating the ability of the proposed system to successfully overcome the impairments due to mobile terrestrial channels, like multipath and shadow fading. For short range applications, Time-Division Multiplexing (TDM) is an efficient way to share the radio resource between multiple terminals. The main modulation parameters for a TDM system are discussed and it is shown that the 802.16a TDM OFDM physical layer fulfills the application requirements; some practical examples are given. A pre-distortion method is proposed that exploit the reciprocity of the radio channel to perform a partial channel inversion achieving improved performances with no modifications of existing receivers.

EPFL2005

Parallel architecture for high-speed analog-to-digital conversion

Guillaume Ding

Nowadays digital signal processing systems used for radar applications, communication systems or RF measurement equipments, require very high sample-rates. Sometimes these sample-rates are beyond the possibilities offered by conventional ADCs. To overcome these limits parallel architectures have been developed. The most commonly used it the one called "time-interleaved" conversion. This technique allows to achieve very-high sample-rates with circuits working at a lower frequency. The accuracy of "time-interleaved" systems is sensitive to sample-time errors. Some calibration techniques have been developed to reduce this sensitivity. They involve very sophisticated digital signal processing and, in most of the cases, they are not directly implemented on silicon but applied on measurement results in software. The goal of this thesis is to study the feasibility of a new parallel architecture for analog-to-digital conversion. This architecture must present a higher robustness to sample-time errors. The first part of this work is dedicated to time-interleaved converter. An analysis of their sensitivity to several imperfections, such as mismatches and systematic and random sample-time error is presented. This analysis is followed by a description of time-interleaved converter evolution, since the first implemented prototype to the current state of the art of the domain. The second part of this thesis focuses on the development of the new conversion technique called "frequency-interleaved". Two different approaches are studied: the first one is based on a Fourier series decomposition of the signal to convert and the second one is based on a Walsh series decomposition. During this study, theoretical and practical aspects are faced the one with the other, to combine signal processing and microelectronics together. It appears that the Fourier series approach offers modest performances and presents serious problems of implementation. Based on this study, the design of functional blocks of a Walsh series based system is proposed.

EPFL2009

A Programmable Receiver for Communication Systems and Its Application to Impulse Radio

Cyril Botteron, Frédéric Chastellain, Pierre-André Farine

The design of a programmable receiver for an ultra wideband (UWB) communication is presented. The receiver is using a fast analog to digital converter (ADC) and a field programmable gate array (FPGA) allowing a rapid performance evaluation for various system architectures and signal processing algorithms. To demonstrate the performance and the versatility of the receiver, a simple communication system and a localization system are implemented. The accuracy of the latter is presented for an indoor environment.