Publication

High-Performance Back-Illuminated Three-Dimensional Stacked Single-Photon Avalanche Diode Implemented in 45-nm CMOS Technology

Publications associées (37)

À propos
Confidentialité
Mentions légales

Graph Chatbot

Chattez avec Graph Search

Posez n’importe quelle question sur les cours, conférences, exercices, recherches, actualités, etc. de l’EPFL ou essayez les exemples de questions ci-dessous.

AVERTISSEMENT : Le chatbot Graph n'est pas programmé pour fournir des réponses explicites ou catégoriques à vos questions. Il transforme plutôt vos questions en demandes API qui sont distribuées aux différents services informatiques officiellement administrés par l'EPFL. Son but est uniquement de collecter et de recommander des références pertinentes à des contenus que vous pouvez explorer pour vous aider à répondre à vos questions.

Connectez-vous pour utiliser Chat avec Graph Search

High-Performance Back-Illuminated Three-Dimensional Stacked Single-Photon Avalanche Diode Implemented in 45-nm CMOS Technology

Graph Chatbot

Chattez avec Graph Search

Exploring negative capacitance and neuromorphic devices based on CMOS-compatible ferroelectric HfO2

A hybrid III-V tunnel FET and MOSFET technology platform integrated on silicon

High-Performance III-V MOSFETs and Tunnel-FETs Integrated on Silicon

Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures

Polarity-Controllable Devices and Circuits for Doping-Free 2D Electronics

Exploration of Negative Capacitance Devices and Technologies

Negative Capacitance as Universal Digital and Analog Performance Booster for Complementary MOS Transistors

First Near-Ultraviolet- and Blue-Enhanced Backside-Illuminated Single-Photon Avalanche Diode Based on Standard SOI CMOS Technology

Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures

Experimental g(m)/I-D Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET

High-Performance III-V MOSFETs and Tunnel-FETs Integrated on Silicon

Polarity-Controllable Devices and Circuits for Doping-Free 2D Electronics

A hybrid III-V tunnel FET and MOSFET technology platform integrated on silicon

Exploration of Negative Capacitance Devices and Technologies

Exploring negative capacitance and neuromorphic devices based on CMOS-compatible ferroelectric HfO2

Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures

Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures

Negative Capacitance as Universal Digital and Analog Performance Booster for Complementary MOS Transistors

Experimental g(m)/I-D Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET

First Near-Ultraviolet- and Blue-Enhanced Backside-Illuminated Single-Photon Avalanche Diode Based on Standard SOI CMOS Technology