A Row-Column Accessed Dynamic Element Matching DAC Architecture for SAR ADCs

Capacitor mismatch in high resolution Successive Approximation Register (SAR) Analog to Digital Converters (ADCs) causes non-linearity effects that reduce the Spurious-Free Dynamic Range (SFDR). This paper presents a novel dynamic element matching (DEM) technique aiming at enhancing the SFDR of SAR ADCs. The high resolution capacitive Digital to Analog Converter (DAC) array is considered as a squarematrix where cells are switched on and off according to row and column bit lines. The number of signals to control and scramble is then highly reduced, enabling high speed operation as well. The proposed architecture has been implemented on 10 and 12-bit SAR ADC models in Matlab in order to highlight its performances. Considering a standard deviation of 1.5% for the unit capacitance, this architecture enables to correct the SFDR by more than 10dB in high distortion cases, while allowing high speed operation.