ReRAM From Material Study to CMOS Co-integration

The revolution of information-technology owes to silicon-based complementary-metal-oxide (CMOS) technology. However, CMOS technology approaches its physical limitation hardening the further progress of memory devices as well as computing paradigm requiring great speed, low power dissipation and high efficiency at elevated density feature. Among the emerging technology, resistive random access memory (ReRAM) based on transition-metal oxide is one of the most promising candidates to meet these requirements. The scalability, simplicity, CMOS compatibility and transistor-free topology of metal-oxide based ReRAM enable the realization of fully operational high-density memory devices that can be also implemented with robust CMOS technology to boost computing system functionality. The present dissertation provides an examination of the ReRAM, based on transition-metal oxide as a viable alternative for non-volatile multi-level data storage from proper material selection to heterogeneous implementation with conventional CMOS technologies. In this thesis, we present a practical consideration regarding the ReRAM-CMOS co-integration using tungsten (W) as the ReRAM electrode. W is one of the most promising material to be used as ReRAM electrode for its CMOS-compatibility with the prospect of device integration, scalability, and low-power consumption. However, W has multiple oxide phases that influence profoundly the ReRAM electrical performances. First, we have studied comprehensively the stand-alone W-based ReRAM properties to have an in-depth understanding of the effect of W electrode on ReRAM performances. We have controlled the effect of W oxidation through the insertion of the interfacial layer. The precise modulation of resistance states has been achieved through the adjustment of pulse input parameters and the incorporation of W in switching. Notable improvements in endurance, power consumption, resistance state stabilization, cycle-to-cycle, and device-to-device variability are reported. Switching kinetics and conductive nano-filament (CNF) evolution is studied in details to understand the microscopic effect of the interface modifications. We also proposed a technique for the nm-scale heterogeneous ReRAM-CMOS co-integration based on using W via from CMOS 180nm technology. The co-integrated stacks show self-limiting behavior with an operating current less than 1mA. The process optimization and stack engineering have been carried out to obtain high device functionality. The results of the best performed integrated (W/Al2O3 (3nm)/HfO2 (5nm)/TiN) ReRAM were further supported by HRTEM-EDX microstructural characterization and electrical performance simulation. Moreover, we have studied the potential of high ion conductive CGO and YSZ thin films to be used as the ReRAM switching layer. Both materials exhibited stable switching performance and great endurance. The formation of multi-filament for CGO and single-filament for YSZ have been proposed as the switching mechanism supported by the electrical characterization. The further scaling process optimization and stack engineering have been performed on the CGO-based ReRAM. For the first time, the outstanding electrical characteristics have been achieved for the (Pt/CGO (14nm) /Al (3nm) /TiN), including operating voltage of (-2 to 1V) at 150uA, high endurance of 10^5 with the 100us pulse width and the capability of multi-level switching by the careful pulse programming operation.