Reconfigurable optical generation of nine Nyquist WDM channels with sinc-shaped temporal pulse trains using a single microresonator-based Kerr frequency comb
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A novel identification and digital predistortion scheme of weakly nonlinear passband systems such as RF power amplifiers (PA) is presented. It is well known that for the identification of weakly nonlinear systems, despite the spectral regrowth, it suffices ...
Many communication systems are {\em bandwidth-expanding}: the transmitted signal occupies a bandwidth larger than the {\em symbol rate}. The sampling theorems of Kotelnikov, Shannon, Nyquist et al. shows that in order to represent a bandlimited signal, it ...
An ultra low power 8-bit current-mode successive approximation (SAR) analog-to-digital (ADC) converter for Wireless Sensor Network (WSN) applications is presented. The proposed ADC contains a new asynchronous clock generator, which works only during data p ...
In wireless portable applications, a large part of the signal processing is performed in the digital domain. Digital circuits show many advantages. The power consumption and fabrication costs are low even for high levels of complexity. A well established a ...
Ultra low power circuits are in high demand in many applications especially in wireless sensor networks (WSN), where energy is scavenged from environment. WSN systems contain different blocks, such as: sensors, filters, analog-to-digital converters, very o ...
Sampling theory has prospered extensively in the last century. The elegant mathematics and the vast number of applications are the reasons for its popularity. The applications involved in this thesis are in signal processing and communications and call out ...
The transceivers of a wireless sensor network (WSN) have to fulfill the low-power and low-voltage constraints. The WiseNET project has already proven that it is possible to design a receiver working at 1V and consuming less than 2mW. However this transceiv ...
This paper describes the implementation of a 12-bit 230 MS/s pipelined ADC using a conventional 1.8V, 0.18μm digital CMOS process. Two-stage folded cascode OTA topology is used for improved settling performance. Extreme low-skew (less than 3ps peak-to-peak ...