Low-power and low-voltage delta-sigma analog-to-digital converters for digital radio in standard CMOS technology

The transceivers of a wireless sensor network (WSN) have to fulfill the low-power and low-voltage constraints. The WiseNET project has already proven that it is possible to design a receiver working at 1V and consuming less than 2mW. However this transceiver is using OOK and wideband FSK modulations, which have a very poor spectral efficiency. A more complex modulation scheme is therefore needed, which requires an ADC in order to demodulate the signal in the digital domain. The ADC is then becoming the main bottleneck if the low-power consumption is targeted. This thesis aims at studying a next generation WiseNET transceiver using a more spectral efficient phase modulation scheme, particularly the new IEEE 802.15.4 standard, and it focuses on the design of a low-power and low-voltage ADC. The choice of the best receiver architecture depends on many factors, among which the power consumption, the integration suitability, the image rejection, the flicker and quantization noise, etc. Several architectures are analyzed in order to identify the trade-offs and select the most suitable for the IEEE 802.15.4 standard, i.e. a low-IF receiver with a quadrature band-pass ΔΣ modulator. From these considerations, a 2nd-order continuous-time quadrature band-pass ΔΣ modulator was implemented in a 0.18μm standard digital process. The design is focused on the constraints of low power consumption, low supply voltage and low complexity imposed by WSN. The availability of I and Q signals in the low-IF receiver enables a quadrature architecture, which allows to combine signal filtering, image rejection and quantization noise reduction. A continuous-time Gm-C implementation further combines the anti-alias function within the ADC and allows to achieve the 1V operation. The quadrature ΔΣ modulator is clocked at 72MHz and the center frequency is set to 3.75MHz with a bandwidth of 3MHz. The maximum measured signal-to-noise ratio is 36dB and the power consumption is only 450μW under 1V.

Hybrid continuous-discrete-time multi-bit delta-sigma A/D converters with auto-ranging algorithm

Sergio Pesenti

In wireless portable applications, a large part of the signal processing is performed in the digital domain. Digital circuits show many advantages. The power consumption and fabrication costs are low even for high levels of complexity. A well established and highly automated design flow allows one to benefit from the constant progress in CMOS technologies. Moreover, digital circuits offer robust and programmable signal processing means and need no external components. Hence, the trend in consumer electronics is to further reduce the part of analog signal processing in the receiver chain of wireless transceivers. Consequently, analog-to-digital converters with higher resolutions and bandwidths are constantly required. The ultimate goal is the direct digitization of radio frequency signals, where the conversion would be performed immediately after the front-end amplifier. ΔΣ-modulation-based converters have proved to be the most suitable to achieve the required performance. Switched-capacitor implementations have been widely used over the last two decades. However, recent publications and books have shown that continuous-time architectures can achieve the same performance with lower power consumption. Most designs found throughout the literature use a single- or few-bit internal quantizer with a high-order modulation. As a result, in order to achieve the resolutions and bandwidths required today, the sampling frequency must exceed 100MHz. This approach leads to non-negligible power consumption in the clock generation. Moreover, the presence of such fast squared signals is not suitable for a system-on-chip comprising radio frequency receivers. In this thesis we propose a low-power strategy relying on a large number of internal levels rather than on a high sampling frequency or modulation order. Besides, a hybrid continuous-discrete-time approach is used to take advantage of the accuracy of switched-capacitor circuits and the low power consumption of continuous-time implementation. The sensitivity to clock jitter brought about by the continuous-time stage is reduced by the use of a large number of levels. An auto-ranging algorithm is developed in this thesis to overcome the limitation of a large-size quantizer under low-voltage supply. Finally, the strategy is applied to a design example addressing typical specifications for a Bluetooth receiver with direct conversion.

EPFL2007

A Low-Power, Low Data-Rate, Ultra-Wideband Receiver Architecture for Indoor Wireless Systems

Cyril Botteron, Frédéric Chastellain, Pierre-André Farine, Alexander Heubi, Christian Robert, Paul Saad, Uroschanit Yodprasit

Abstract—In this paper, a novel architecture for a low data-rate, low power consumption Impulse Radio (IR) Ultra- Wideband (UWB) receiver is presented in which the received UWB signal is downconverted to a given intermediate frequency (IF) rather than at baseband. This way, the requirement to implement two separate paths for the in-phase and the quadrature components is removed and the power consumption can be reduced. From the IF, the signal is converted to the digital domain by a set of 24 Redundant Signed Digit (RSD) Analog to Digital Converters (ADCs) working at the pulse repetition rate. The digitized signal is then correlated with a predefined template prior to be fed to the bit detector. The trade-offs for the selection of the IF are highlighted and the BER performance of the proposed receiver is evaluated using simulations in 802.15.3a multipath channels. The expected power consumption for the implementation of the receiver using a CMOS process is also provided.

2008

Design of a 2.4 Ghz BAW-Based CMOS Transmitter

Matteo Contaldo

In recent years, bulk acoustic wave resonators (BAW) in combination with RF circuits have shown a big potential in achieving the low-power consumption and miniaturization level required to address wireless sensor nodes (WSN) applications. A lot of work has been focused on the receiver side, by integrating BAW resonators with low noise amplifiers (LNA) and in frequency synthesis with the design of BAW-based local oscillators, most of them working at fixed frequency due to their limited tuning range. At the architectural level, this has forced the implementation of several single channel transceivers. This thesis aims at exploring the use of BAW resonators in the transmitter, proposing an architecture capable of taking full advantage of them. The main objective is to develop a transmitter for WSN multi-channel applications able to cover the whole 2.4 GHz ISM band and enable the compatibility with wide-spread standards like Bluetooth and Bluetooth Low Energy. Typical transmissions should thus range from low data rates (typically tens of kb/s) to medium data rates (1 Mb/s), with FSK and GFSK modulation schemes, should be centered on any of the channels provided by these standards and cover a maximum transmission range of some tens of meters. To achieve these targets and circumvent the limited tuning range of the BAW oscillator, an up-conversion transmitter using wide IF is used. The typical spurs problems related to this transmitter architecture are addressed by using a combined suppression based on SSB mixing and selective amplification. The latter is achieved by cointegration of a high efficiency power amplifier with BAW resonators, which allows performing spurs filtering while preserving the efficiency. In particular the selective amplifier is designed by including in the PA analysis the BAW resonator parameters, which allows integrating the BAW filter into the passive network loading the amplifier, participating in the drain voltage shaping. Finally, the frequency synthesis section uses a fractional division plus LC PLL filtering and further integer division to generate the IF signals and exploit the very-low BAW oscillator phase noise. The transmitter has been integrated in a 0.18 µm standard digital CMOS technology. It allows addressing the whole 80 MHz wide 2.4 GHz ISM band. The unmodulated RF frequency carrier demonstrates a very-low phase noise of –136 dBc/Hz at 1 MHz offset. The IF spurs are maintained lower than –48 dBc, satisfying the international regulations for output power up to 10 dBm without the use of any quadrature error compensation in the transmitter. This is achieved thanks to the rejection provided by the SSB mixer and the selective amplifier, which can reach drain efficiency of up to 24% with integrated inductances, including the insertion losses of the BAW filter. The transmitter consumes 35.3 mA at the maximum power of 5.4 dBm under 1.6 V (1.2 V for the PA), while transmitting a 1 Mb/s GFSK signal and complying with both Bluetooth and Bluetooth Low Energy relative and absolute spectrum requirements.