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GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI

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GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI

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2D Nanosystems: Applications of 2D Semiconductors for In-Memory Computing

Miss-Optimized Memory Systems: Turning Thousands of Outstanding Misses into Reuse Opportunities

GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI

Gain-Cell Embedded DRAMs: Modeling and Design Space

Gain-Cell Embedded DRAMs: Modeling and Design Space

In Search of Lost Bandwidth: Extensive Reordering of DRAM Accesses on FPGA

A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications

A Real-Time Multi-Camera Depth Estimation ASIC with Custom On-Chip Embedded DRAM

Data-Retention-Time Characterization of Gain-Cell eDRAMs across the Design and Variations Space

Exploration of Negative Capacitance Devices and Technologies

2D Nanosystems: Applications of 2D Semiconductors for In-Memory Computing

Exploration of Negative Capacitance Devices and Technologies

Data-Retention-Time Characterization of Gain-Cell eDRAMs across the Design and Variations Space

GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI

A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications

Miss-Optimized Memory Systems: Turning Thousands of Outstanding Misses into Reuse Opportunities

In Search of Lost Bandwidth: Extensive Reordering of DRAM Accesses on FPGA

A Real-Time Multi-Camera Depth Estimation ASIC with Custom On-Chip Embedded DRAM

Gain-Cell Embedded DRAMs: Modeling and Design Space

Gain-Cell Embedded DRAMs: Modeling and Design Space