Modeling for Ultra Low Noise CMOS Image Sensors

The low-light performance of a CMOS image sensor (CIS) is one of the most important performance metrics in a camera, whether it is used in products for consumer electronics or in an image-acquisition system for machine vision or the Internet-of-Things (IoT). At very low levels of illumination, the image sensors are limited by the noise generated by the readout circuits used to convert the information stored in the photodetector element, the pinned photodiode (PPD). Thanks to the development of efficient noise reduction techniques, modern CISs offer extremely interesting performance with sub-electron input-referred noise values. However, further noise reduction is needed to enable the single photon counting capability, which will allow new opportunities in a large variety of scientific applications.

This thesis focuses on the modeling of ultra-low noise CISs by exploring two main research topics. The first is the modeling of the PPD device together with the transfer gate (TG). The interface between these two structures limits performance in many advanced applications and requires a deep understanding of the charge transfer process. The core of the first compact model for the charge transfer in PPDs is reported here. The second evaluates the impact of different techniques on total noise reduction. In particular, the in-pixel source follower (SF) optimization, the combination of the column-level gain with the correlated multiple sampling (CMS) order and the effect of technology downscaling are analyzed and then verified by software simulations and experimental results.

The core of a physics-based compact model for the charge transfer in PPDs for CIS is presented in this dissertation. A set of analytical expressions is derived for the 2D electrostatic profile, the PPD capacitance, and the charge transfer current. The proposed model relies on the thermionic emission current mechanism, the barrier modulation and the full-depletion approximation to obtain the charge transfer current. The model is fully validated with stationary and opto-electrical technology computer-aided design (TCAD) simulations. The charge transfer model is validated experimentally by the expression of the total amount of the transferred charges derived from the charge transfer current and evaluated for different values of light intensity, TG voltage and transfer time. The result is a proven resource for CIS pixel designers in the analysis, simulation and optimization of PPD-based pixel in CISs.

The main circuit-level technique for noise reduction studied in this thesis is the CMS, which is used to reduce the thermal noise and the residual flicker noise originated in the in-pixel SF. To verify the impact of the combination of the column-level gain and the analog CMS on the readout noise, a readout chain with variable gain and variable CMS order has been integrated in a standard 180 nmCIS process. The match between the measurement and the noise model results validates experimentally the model itself. Based on transient noise simulation results, the combination of an optimized pMOS source follower (SF), a column-level gain equal to 64 and a CMS of order 8 allows the noise to be reduced to the value of 0.20 erms, with a readout time of 43 us.

Ultra Low Noise CMOS Image Sensors

Assim Boukhayma

CMOS Image Sensors (CIS) overtook the charge coupled devices (CCDs) in low noise performance. Photoelectron counting capability is the next step for CIS for ultimate low light performance and new imaging paradigms. This work presents a review of CMOS image sensors based on pinned photo diodes (PPDs). The latter includes the historical background, the PPD physics and the readout chain circuits used for low-noise performance. The physical mechanisms behind the random fluctuations affecting the signal at different levels of conventional CIS readout chains are reviewed and clarified. This thesis dedicates a particular focus to the readout circuit noise given that it precludes photoelectron counting in conventional CIS. A detailed analytical calculation of the temporal read noise (TRN) in conventional CIS readout chain is presented. The latter suggests different noise reduction techniques at process and circuit design level. Among the noise reduction techniques suggested by the analytical noise calculation, the increase of the oxide capacitance by using a thin oxide in-pixel amplifying transistor, for low 1/f noise, is suggested for the first time. A test chip designed in a 180 nm CIS process and embedding optimized readout chains exploiting the new pixels together with state-of-the-art 4T pixels optimized at process level for low 1/f noise. A mean input-referred noise of 0.4 e-rms has been measured. Compared with the state-of-the-art pixels, also present onto the test chip, the mean RMS noise is divided by more than 2. Based on these encouraging result, a full VGA (640H×480V) imager has been integrated in a standard CIS process. The presented imager relies on a 4T pixel of 6.5 µm pitch with a properly sized and biased thin oxide PMOS source follower. A full characterization of the proposed image sensor, at room temperature, is presented. The sensor chip features an input-referred noise histogram from 0.25 e-rms to a few e-rms peaking at 0.48 e-rms. This sub-0.5 electron noise performance is obtained with a full well capacity of 6400 e- and a frame rate that can go up to 80 fps. The VGA imager also features a fixed pattern noise as low as 0.77%, a lag of 0.1% and a dark current of 5.6 e-/s. Correlated multiple sampling (CMS) is a noise reduction technique commonly used in low noise CIS. This work presents an original design for CMS based on a passive switched-capacitor network, with a minimum number of capacitors. The proposed circuit requires no additional active circuitry, has no impact on the output dynamic range and does not need multiple analog-to-digital conversions. It was verified with transient noise simulations and shows a noise reduction in perfect agreement with ideal CMS. For a future perspective, the impact of the technology downscale on CIS sensitivity from an electronic read noise aspect is investigated. Active imaging in the Terahertz (THz) band is an emerging technology. Source modulation combined with a selective filtering can be used to reduce the noise in CMOS THz imagers. This work presents the first integration of a 1 kpixel CMOS THz imager integrating, in each pixel, a metal antenna with a MOS rectifier, low noise amplification and highly selective filtering, based on a switch-capacitor N-path filter combined with a broad band Gm-C filter. The latter has been tested successfully. An input-referred noise of 0.2 µV RMS corresponding to a total noise equivalent THz power of 0.6 nW at 270 GHz and 0.8 nW at 600 GHz.

EPFL2016

A Switched Capacitor Fully Differential Correlated Double Sampling Circuit for CMOS Image Sensors

Sandro Carrara, Gözen Köklü, Yusuf Leblebici

Complementary metal oxide semiconductor (CMOS) image sensors are more compatible than charge coupled devices (CCDs) for lab-on-a-chip platforms due to their inherited advantages. However, without the noise reduction circuits, CMOS technology wouldn’t be able to compete with CCDs. Today, correlated double sampling circuits (CCDs) are used in all CMOS imagers in order to remove the reset noise and the fixed pattern noise. However, these circuits immensely decrease the fill factor of the image sensors because of their large area and their requirement of extra circuitries in order to convert their single ended outputs to differential outputs. In this paper, we propose a CDS architecture convenient for CMOS imagers that uses switched capacitor fully differential configuration which reduces the noise in the same way as the conventional CDS architectures while decreasing the area and increasing the fill factor.

2011

Smart Imaging and On-Focal-Plane Image Acquisition and Processing in Standard CMOS Technology

Nikola Katic

In recent years, modern imaging sensors and systems have become increasingly complex following the growing demand for high-quality and high-resolution imaging. Commercially available sensors having 30-40 mega-pixel resolutions are common nowadays, while professional and scientific imaging systems (e.g. telescope and satellite sensors) often have hundreds of mega-pixels or even giga-pixel resolution. Such sensors or multi-sensor systems generate extreme amounts of data and require an excessive amount of power in order to process and stream-out the acquired data at the required speed. Consequently, three difficult and closely related bottlenecks appear in such systems: power consumption, data bandwidth and memory storage. Nevertheless, the vast majority of applications (such as machine vision, bio-medical, surveillance, space imaging, etc.) do not process all the data acquired from the conventional image acquisition. In fact, most of the image (video) data is extremely redundant in both temporal and spatial domain. Moreover, in many of these applications, this excessive data is simply discarded despite the additional resources that were used to acquire it. This Thesis explores new and and "smart" ways of image acquisition that can exploit this redundancy and reduce the required image data. The ultimate goal of the research conducts into reducing the power consumption, system bandwidth, memory requirements and improve the overall system efficiency in numerous modern image acquisition applications. The main focus of this Thesis is the investigation of three unconventional approaches to image acquisition that offer power, bandwidth and memory storage reduction. All three methods are explored in the context of CMOS integrated circuit implementation directly on the focal-plane in order to maximize their efficiency. The first investigated method is called "relative imaging" (RI). The image sensor detects the relative ratios of the photo-currents corresponding to the neighboring pixels without performing pixel integration. This method allows high frame-rates with a very high dynamic range. Moreover, detecting the photo-current ratios (instead of the absolute amplitudes) corresponds better to the intrinsic nature of VLSI design. The second investigated method which enables the reduction of the required image information is compressive sampling (CS). Compressive sampling exploits image sparsity in order to reduce the amount of information that is required to guarantee correct image reconstruction. The third method, multi-band edge detection (MBED), decomposes the image content into separate frequency bands and performs single-bit quantization of each frequency band separately. It achieves 1-1.33 bit-per-pixel compression level, while preserving most of the image information and demonstrating robust performance in the presence of noise and other physical non-idealities. An additional focus of this Thesis is the design of unconventional analog-to-digital converter (ADC) topologies convenient for "smart" image acquisition.