Modeling for Ultra Low Noise CMOS Image Sensors

The low-light performance of a CMOS image sensor (CIS) is one of the most important performance metrics in a camera, whether it is used in products for consumer electronics or in an image-acquisition system for machine vision or the Internet-of-Things (IoT). At very low levels of illumination, the image sensors are limited by the noise generated by the readout circuits used to convert the information stored in the photodetector element, the pinned photodiode (PPD). Thanks to the development of efficient noise reduction techniques, modern CISs offer extremely interesting performance with sub-electron input-referred noise values. However, further noise reduction is needed to enable the single photon counting capability, which will allow new opportunities in a large variety of scientific applications.

This thesis focuses on the modeling of ultra-low noise CISs by exploring two main research topics. The first is the modeling of the PPD device together with the transfer gate (TG). The interface between these two structures limits performance in many advanced applications and requires a deep understanding of the charge transfer process. The core of the first compact model for the charge transfer in PPDs is reported here. The second evaluates the impact of different techniques on total noise reduction. In particular, the in-pixel source follower (SF) optimization, the combination of the column-level gain with the correlated multiple sampling (CMS) order and the effect of technology downscaling are analyzed and then verified by software simulations and experimental results.

The core of a physics-based compact model for the charge transfer in PPDs for CIS is presented in this dissertation. A set of analytical expressions is derived for the 2D electrostatic profile, the PPD capacitance, and the charge transfer current. The proposed model relies on the thermionic emission current mechanism, the barrier modulation and the full-depletion approximation to obtain the charge transfer current. The model is fully validated with stationary and opto-electrical technology computer-aided design (TCAD) simulations. The charge transfer model is validated experimentally by the expression of the total amount of the transferred charges derived from the charge transfer current and evaluated for different values of light intensity, TG voltage and transfer time. The result is a proven resource for CIS pixel designers in the analysis, simulation and optimization of PPD-based pixel in CISs.

The main circuit-level technique for noise reduction studied in this thesis is the CMS, which is used to reduce the thermal noise and the residual flicker noise originated in the in-pixel SF. To verify the impact of the combination of the column-level gain and the analog CMS on the readout noise, a readout chain with variable gain and variable CMS order has been integrated in a standard 180 nmCIS process. The match between the measurement and the noise model results validates experimentally the model itself. Based on transient noise simulation results, the combination of an optimized pMOS source follower (SF), a column-level gain equal to 64 and a CMS of order 8 allows the noise to be reduced to the value of 0.20 erms, with a readout time of 43 us.