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Power-Hardware-In-the-Loop (PHIL) setups have gained high importance in validation of the performance of newly developed algorithms and devices with low risk and implementation cost. However, the interconnection of a power hardware with a simulated model via a feedback loop may make the closed-loop system unstable. In this paper, a systematic method is proposed to design a digital filter such that the closed-loop stability of PHIL setup is guaranteed and its performance is optimised. The design of the filter is formulated as a specific controller synthesis problem that maximises the accuracy and ensures a certain robustness margin. The design problem is written as a convex optimization and solved efficiently using available solvers. Due to the data-driven characteristic of the proposed method, there is no need for the model of the Hardware Under the Test (HUT) to guarantee the stability and performance. This method is also extended to a multi-scenario case including different combinations of hardware and simulated systems. The PHIL experimental results validate the performance of the proposed method while satisfying the required stability margin and improving the accuracy significantly compared to conventional filters.
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Drazen Dujic, Andrea Cervone, Tianyu Wei