In-depth Cryogenic Characterization of 22 nm FDSOI Technology for Quantum Computation

Edoardo Charbon, Christian Enz, Hung-Chi Han, Farzan Jazaeri
IEEE, 2021
Article de conférence

In this paper, the influence of temperature and back-gate bias is experimentally investigated on 22 nm FDSOI CMOS process. Cryogenic DC characterization was carried out under various back-gate voltages, V back , from 2.95 K back to 300 K. An abrupt drop-off in drain current due to intersubband scattering is experienced in the transfer characteristic with a certain V back . Moreover, resonant and source-to-drain tunneling transports are observed in devices with minimal channel length at cryogenic temperatures. The threshold voltage, V T , and free carrier mobility, µ eff , and their dependence on the back-gate voltage over a wide range of temperatures are extracted and discussed in detail. This work aims at investigating the impact of back gate potential on V T and carrier transport at cryogenic temperatures, further paving the way towards up-scaling of quantum computers.

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Edoardo Charbon, Christian Enz, Hung-Chi Han, Farzan Jazaeri
IEEE, 2021
Article de conférence

Résumé

Official source

https://infoscience.epfl.ch/record/289796?ln=fr

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Concepts associés

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Towards a scalable quantum computer

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A quantum machine may solve some complex problems that are intractable for even the most powerful classical computers. By exploiting quantum superposition and entanglement phenomena, quantum algorithms can achieve from polynomial to exponential speed up when compared to their best classical counterparts. A quantum computer will be a part of a heterogeneous, multi-core computer in which a classical processor will interact with several accelerators such as FPGAs, GPUs and also a quantum co-processor. Figure 1 shows the different layers of the quantum computer system stack [1]. Building such a quantum system requires contributions from different fields such as physics, electronics, computer science and computer engineering for addressing the following challenges: i) build scalable quantum chips integrating qubits with long coherence times and high-fidelity operations, ii) develop classical control electronics at possibly cryogenic temperatures and iii) create the microarchitecture as well as the software for quantum computation.

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Cryogenic device models are essential for the reliable design of the cryo-CMOS interface that enables large-scale quantum computers. In this paper, mismatch characterization and modeling of a 40-nm bulk CMOS process over the 4.2-300 K temperature range is studied, towards an all-operating-region mismatch model. An overall increase of variability is shown, in particular in the subthreshold region at cryogenic temperatures due to a dramatic increase of the subthreshold slope mismatch. Mismatch in strong inversion is modeled by the Croon model while the weak-inversion region is modeled by taking subthreshold slope variability into account. This results in the first model capable of predicting mismatch over the whole range of operating regions and temperatures.

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CMOS circuits operating at cryogenic temperature (cryo-CMOS) are required in several low-temperature applications. A compelling example is the electronic interface for quantum processors, which must reside very close to the cryogenic quantum devices it serves, and hence operate at the same temperature, so as to enable practical large-scale quantum computers. Such cryo-CMOS circuits must achieve extremely high performance while dissipating minimum power to be compatible with existing cryogenic refrigerators. These requirements asks for cryo-CMOS electronics on par with or even exceeding their room temperature counterparts. This paper overviews the challenges and the opportunities in designing cryo-CMOS circuits, with a focus on analog and mixed-signal circuits, such as voltage references and data converters.

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