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Associativity-agnostic in-cache computing memory architecture optimized for multiplication

Publications associées (32)

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Approximate Computing With Unreliable Dynamic Memories

Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman, Georgios Karakonstantis, Shrikanth Ganapathy

Embedded memories account for a large fraction of the overall silicon area and power consumption in modern SoC(s). While embedded memories are typically realized with SRAM, alternative solutions, such as embedded dynamic memories (eDRAM), can provide highe ...

2015

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With the end of Dennard scaling, server power has emerged as the limiting factor in the quest for more capable datacenters. Without the benefit of supply voltage scaling, it is essential to lower the energy per operation to improve server efficiency. As th ...

2014

Using Managed Runtime Systems to Tolerate Holes in Wearable Memories

James Richard Larus

New memory technologies, such as phase-change memory (PCM), promise denser and cheaper main memory, and are expected to displace DRAM. However, many of them experience permanent failures far more quickly than DRAM. DRAM mechanisms that handle permanent fai ...

ACM2013

A Distributed Interleaving Scheme for Efficient Access to WideIO DRAM Memory

Giovanni De Micheli, Luca Benini, Ciprian Seiculescu

Achieving the main memory (DRAM) required bandwidth at ac- ceptable power levels for current and future applications is a ma- jor challenge for System-on-Chip designers for mobile platforms. Three dimensional (3D) integration and 3D stacked DRAM mem- ories ...

2012

System of nano-silver inkjet printed memory cards and PC card reader and programmer

Alexandru Rusu, Suat Ayoz

This work describes the development of inkjet printed, low-cost memory cards, and complementary pair of memory card reader and card reader/programmer for PCs. This constitutes a complete system that can be used for various applications. The memory cards ar ...

Elsevier2011

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In the present work a punch-through impact ionization MOSFET (PIMOS) is presented, which exploits impact ionization in low-doped body-tied [Omega]- and tri-gate structures to obtain abrupt switching (3-10 mV/decade) combined with a hysteresis in the ID(VDS ...

2008

Abrupt current switching due to impact ionization effects in Ω-MOSFET on low doped bulk silicon

Mihai Adrian Ionescu, Didier Bouvet, Kirsten Emilie Moselund, Vincent Pott

In this paper, we report very abrupt current switching and hysteresis effects due to saddle point and impact ionization in low doped n-channel Omega-Gate MOSFET (Ω-MOSFET). The Ω-MOSFETs are fabricated on low-doped (8×1014cm-3) bulk silicon by bulk silicon ...

2008

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This work reports on memory applications of punch-through impact ionization single-transistor latch (PIMOS), showing abrupt current switching (3-10mV/dec.) as well as hysteresis in both ID(VDS) and ID(VGS). A capacitor-less 1PIMOS - 1 MOSFET DRAM memory is ...

2008

Semiconductor memory cell, array, architecture and device, and method of operating same

Serguei Okhonin

There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory cell and technique of reading data from and writing data into that memory cell. In this regard, in one embodiment of this aspect of ...

2007

Abrupt current switching due to impact ionization effects in Omega-MOSFET on low doped bulk silicon

Mihai Adrian Ionescu, Didier Bouvet, Kirsten Emilie Moselund, Vincent Pott

In this paper, we report very abrupt current switching and hysteresis effects due to saddle point and impact ionization in low doped n-channel Omega-Gate MOSFET (Omega-MOSFET). The Omega-MOSFETs are fabricated on low-doped (8x10(14)cm(-3)) bulk silicon by ...

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