Publication
Systems and circuits are described for transmitting data over physical channels to provide a fault tolerant, high speed, low latency interface such as between a memory controller and memory devices. Communications signals are communicated over interconnection groups comprised of multiple wires, with the described encoding and decoding permitting continued communication in the presence of a wire failure within an interconnection group. An efficient distributable voltage regulator to provide communications driver power is also disclosed.
Aleksandra Radenovic, Andras Kis, Mukesh Kumar Tripathi, Zhenyu Wang, Asmund Kjellegaard Ottesen, Yanfei Zhao, Guilherme Migliato Marega, Hyungoo Ji
Andras Kis, Guilherme Migliato Marega