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Fab-to-fab and run-to-run variability in 130 nm and 65 nm CMOS technologies exposed to ultra-high TID

Publications associées (44)

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Total ionizing dose effects on a 28 nm Hi-K metal-gate CMOS technology up to 1 Grad

Chunmin Zhang, Alessandro Pezzotta

This paper presents the results of an irradiation study on single transistors manufactured in a 28 nm high-k commercial CMOS technology up to 1 Grad. Both nMOSFET and pMOSFET transistors have been irradiated and electrical parameters have been measured. Fo ...

2017

Thermal aware design and comparative analysis of a high performance 64-bit adder in FD-SOI and bulk CMOS technologies

Yusuf Leblebici

Thermal behaviours of high-performance digital circuits in bulk CMOS and FDSOI technologies are compared on a 64-bit Kogge-Stone adder designed in 40nm CMOS node. Temperature profiles of the adder in bulk and FDSOI are extracted with thermal simulations an ...

Elsevier Science Bv2017

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This paper presents a microwave noise source implemented in a commercial CMOS technology. The circuit is based on the avalanche noise generated by both the source-to-bulk and the drain-to-bulk junctions in reverse breakdown. Two sources of different juncti ...

Institute of Electrical and Electronics Engineers2016

Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS

Andreas Peter Burg, Pascal Andreas Meinerzhagen, Oskar Andersson

In this study, design considerations for ultra low voltage (ULV) standard-cell based memories (SCM) are presented. Trade-offs for area cost, leakage power, access time, and access energy are discussed and realized using different read logic styles, latch a ...

Institute of Electrical and Electronics Engineers2016

Design methodology for low power RF LNA based on the figure of merit and the inversion coefficient

Christian Enz

The complexity of radiofrequency circuit design comes from the large number of parameters to be adjusted. Constant node shrink in CMOS process and variation of technology skills significantly contribute to this complexity. The paper reports on a reliable a ...

Springer2016

Fabrication of nanoporous membranes through silicon templates : two different approaches

Philippe Renaud, Arnaud Bertsch, Niccolo Piacentini, Stefano Silvio Giovanni Varricchio

We present here a novel approach to fabricate nanoporous membranes based on the use of sacrificial template structures to individually define pore parameters such as geometry, shape, and placement. Based on this rationale two different nano-fabrication met ...

2016

The aim of this work has been the investigation of homo-junction Tunnel Field Effect Transistors starting from a compact modelling perspective to its possible applications. Firstly a TCAD based simulation study is done to explain the main device characteri ...

EPFL2015

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A 2.4 GHz polar transmitter compliant with the IEEE 802.15.6 standard is presented in this paper. A Linearized class-C power amplifier, employing dynamic biasing is used to minimize the adjacent channel interference and satisfy the defined spectrum mask re ...

IEEE2015

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A 2.4 GHz low power polar transmitter is proposed in this paper. A dynamic biasing circuit, controlled by a digital envelope signal, is used as a direct digital-to-RF envelope converter. It effectively linearizes the input-output characteristic of the over ...

Springer Verlag2014

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A 90GS/s 8b low-power ADC is presented achieving 33.0-36.0dB SNDR and a FoM of 203fJ/conversion-step. High conversion speed of up to 100GS/s and high input bandwidth of 22GHz is achieved by using a 1:64 interleaver with integrated sampling. Single NMOS tra ...

2014