Modelling and design of CMOS SPAD sensors for quantum random number generation

Modern digital connectivity has necessitated the creation of robust methods for securely storing and transferring data. At the heart of all security infrastructure is the random number generator (RNG). While random numbers find use in a variety of applications, from scientific simulation to gambling, it is in the hardware security domain where their performance is most critical. As a fundamental security primitive, the requirements for an RNG are exhaustive. Any practical RNG realization, which extracts entropy from a physical source of randomness, requires intensive modelling, characterization and robustness against environmental changes and adversarial attacks. Existing implementations often rely on heavy levels of post-processing of the digital bits produced to meet performance requirements. Furthermore, with the advent of Quantum Computing, which promises to shatter the security of many existing encryption protocols, the demands placed on RNG designs is fortifying considerably. Quantum random number generators (RNGs) hope to meet those demands. A variety of techniques, that exploit various quantum mechanical phenomena, can be used to generate random numbers. However, many require complex, bulky setups that are not amenable to small form factor implementations or scalability. Single-photon avalanche diodes (SPADs) are a CMOS-compatible modern detector technology, that enable versatile sensing of optical photons. SPAD-based sensors, which have the ability to co-integrate a myriad of digital timing and processing functions, are a promising potential solution for QRNG implementations. This thesis focuses on modelling and design of quantum random bit generators in a 55 nm Bipolor-CMOS-DMOS (BCD) process. First, several new detectors are developed in a 55 nm BCD process. Effective optimization of the designs, without changes to the standard process, are proposed and tested, resulting in excellent noise and sensitivity performance. These detectors are then combined with pixel circuits that exploit photon-timing statistics for generation of random bits. Intensive modelling on bias and modelling is performed. In particular, an analytical method for determining serial correlation of bits, when considering detector dead time and afterpulsing, is proposed and validated with simulation and experiment. Based on the analysis of bias, a dynamic comparator based sampling flip-flop approach, for reduction of bit bias, is introduced as a component in a quantum random flip-flop (QRFF), configuration. This method is compared and contrasted to a first photon-arrival comparison bit generation method. The designs are scaled to SPAD sensor arrays, that when combined with external illumination, function as gigabit-per-second QRNG designs. The FortunaSPAD QRNG is a dual-interface design, capable of a combined output data rate of 3.3 Gbps. The FortunaSPAD2 QRNG sensor implements a macro-pixel design to improve robustness against pixel failure.