A 3.3-Gb/s SPAD-Based Quantum Random Number Generator

Quantum random number generators (QRNGs) are a burgeoning technology used for a variety of applications, including modern security and encryption systems. Typical methods exploit an entropy source combined with an extraction or bit generation circuit in order to produce a random string. In integrated designs, there is often little modeling or analytical description of the entropy source, circuit extraction, and post-processing provided. In this work, we present a single-photon avalanche diode (SPAD)-based QRNG design, which utilizes the quantum random flip-flop (QRFF) method. Extensive modeling of detector and circuit imperfections that result in entropy degradation is performed. A new method to analytically model serial autocorrelations of the proposed bit generation method, which includes detector dead time, is proposed. Then, a Verilog-AMS model is developed in order to validate the analytical model in simulation. A novel transistor implementation of the QRFF circuit is presented, which enables compensation of the degradation in entropy inherent to the finite non-symmetric transitions of the random flip-flop. Finally, a full system containing two independent arrays of the QRFF circuit is manufactured and tested in a 55-nm bipolar-CMOS-DMOS (BCD) technology node, demonstrating bit generation statistics that are commensurate to the developed model. The full chip is able to generate 3.3 Gb/s of data when operated with an external LED. Pixelwise and spatial analysis of bias and correlation is performed. NIST STS (SP 800-22) and SP 800-90B are used to benchmark the generated bit strings.