Publications associées à Comparison of a Timing-Error Tolerant Scheme with a Traditional Re-transmission Mechanism for Networks on Chips

Highly Parallel RTL Simulation

Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

EPFL2024

Contemporary Logic Synthesis: with an Application to AQFP Circuit Optimization

Siang-Yun Lee

Electronic devices play an irreplaceable role in our lives. With the tightening time to market, exploding demand for computing power, and continuous desire for smaller, faster, less energy-consuming, and lower-cost chips, computer-aided design for electron ...

EPFL2024

Error estimates for SUPG-stabilised Dynamical Low Rank Approximations

Fabio Nobile, Thomas Simon Spencer Trigo Trindade

We perform an error analysis of a fully discretised Streamline Upwind Petrov Galerkin Dynamical Low Rank (SUPG-DLR) method for random time-dependent advection-dominated problems. The time integration scheme has a splitting-like nature, allowing for potenti ...

Springer Nature Switzerland2025

Global existence for perturbations of the 2D stochastic Navier-Stokes equations with space-time white noise

Martin Hairer

We prove global in time well-posedness for perturbations of the 2D stochastic Navier-Stokes equations partial derivative( t)u + u center dot del u = Delta u - del p + sigma + xi, u(0, center dot ) = u(0),div (u) = 0, driven by additive space-time white noi ...

Springernature2024

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Sahand Kashani

The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

EPFL2023

Low Power LDPC Decoding by Reliable Voltage Down-Scaling

Andreas Peter Burg

Low-Density Parity-Check (LDPC) decoder is among the power hungry building blocks of wireless communication systems. Voltage scaling down to Near-Threshold (NT) voltages substantially improves energy efficiency, in theory up 10x. However, tuning the voltag ...

IEEE2023

Analysis of the influence of errors in DNA-based image coding

Touradj Ebrahimi, Michela Testolina, Davi Nachtigall Lazzarotto

In the last decade, DNA has been increasingly investigated as an alternative medium for cold data storage, presenting several advantages over standard hard drives such as a higher density, longer lifespan and lower energy consumption. However, such coding ...

2023

WINC: A Wireless IoT Network for Multi-Noise Source Cancellation

Haitham Al Hassanieh, Junfeng Guan, Jiaming Wang

This paper introduces Wireless IoT-based Noise Cancellation (WINC) which defines a framework for leveraging a wireless network of IoT microphones to enhance active noise cancellation in noise-canceling headphones. The IoT microphones forward ambient noise ...

Assoc Computing Machinery2023

Model-based constraints for trajectory determination of quad-copters: Design, calibration & merits for direct orientation

Jan Skaloud, Davide Antonio Cucci, Kenneth Joseph Paul

This paper proposes a novel method to improve georeferencing of airborne laser scanning by improved trajectory estimation using Vehicle Dynamic Model. In Vehicle Dynamic Model (VDM), the relationship between the dynamics of the platform and control inputs ...

2023

Critical Schrodinger Cat Qubit

Vincenzo Savona, Fabrizio Minganti, Luca Gravina

Encoding quantum information onto bosonic systems is a promising route to quantum error correc-tion. In a cat code, this encoding relies on the confinement of the dynamics of the system onto the two-dimensional manifold spanned by Schrodinger cats of oppos ...

AMER PHYSICAL SOC2023