Publication

Spatial: A Language and Compiler for Application Accelerators

Publications associées (30)

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Electronic devices play an irreplaceable role in our lives. With the tightening time to market, exploding demand for computing power, and continuous desire for smaller, faster, less energy-consuming, and lower-cost chips, computer-aided design for electron ...

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Automated Formal Verification of Software Network Functions

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Formally verifying the correctness of software is necessary to merit the trust people put in software systems. Currently, formal verification requires human effort to prove that a piece of code matches its specification and code changes to improve verifiab ...

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Transformer models such as GPT generate human-like language and are predictive of human brain responses to language. Here, using functional-MRI-measured brain responses to 1,000 diverse sentences, we first show that a GPT-based encoding model can predict t ...

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Is the powersave governor really saving power?

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A frequency scaling governor is critical for the performance management of cloud servers, as it enhances energy efficiency and helps to control operational temperatures, thereby ensuring system reliability. However, our in-depth analysis of the application ...

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Highly Parallel RTL Simulation

Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

EPFL2024

Scalable Logic Rewriting Using Don’t Cares

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Logic rewriting is a powerful optimization technique that replaces small sections of a Boolean network with better implementations. Typically, exact synthesis is used to compute optimum replacement on-the-fly, with possible support for Boolean don't cares. ...

2024

X-Attack 2.0: The Risk of Power Wasters and Satisfiability Don’t-Care Hardware Trojans to Shared Cloud FPGAs

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Cloud computing environments increasingly provision field-programmable gate arrays (FPGAs) for their programmability and hardware-level parallelism. While FPGAs are typically used by one tenant at a time, multitenant schemes supporting spatial sharing of c ...

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Decoding electroencephalographic responses to visual stimuli compatible with electrical stimulation

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Electrical stimulation of the visual nervous system could improve the quality of life of patients affected by acquired blindness by restoring some visual sensations, but requires careful optimization of stimulation parameters to produce useful perceptions. ...

Aip Publishing2024

SAT-based Exact Modulo Scheduling Mapping for Resource-Constrained CGRAs

David Atienza Alonso, Giovanni Ansaloni, José Angel Miranda Calero, Juan Pablo Sapriza Araujo, Rubén Rodríguez Álvarez, Benoît Walter Denkinger, Ruben Rodriguez

Coarse-Grain Reconfigurable Arrays (CGRAs) represent emerging low-power architectures designed to accelerate Compute-Intensive Loops (CILs). The effectiveness of CGRAs in providing acceleration relies on the quality of mapping: how efficiently the CIL is c ...

2024

The conceptual foundations of innate immunity: Taking stock 30 years later

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While largely neglected over decades during which adaptive immunity captured most of the attention, innate immune mechanisms have now become central to our understanding of immunology. Innate immunity provides the first barrier to infection in vertebrates, ...

2024