Design Tradeoffs in Ultra-Low-Power Digital Nano-Scale CMOS

In ultra-low-power (ULP) applications, the supply voltage is generally reduced well below threshold voltage of MOS devices in order to limit dissipation and to control the device leakage current due to the subthreshold channel residual current. However, recent studies show that reducing the supply voltage increases the device susceptibility to process variations, resulting in delay spread and decreased noise margin. This article presents an analytical approach for studying the effect of technology scaling and variability on performance of ULP integrated systems. Unlike the conventional design methodologies, we include the effect of process variation on circuit performance in each step of design and optimization. Here, the power dissipation and noise margin are both calculated as a function of turn-on and turn-off current of devices. This approach helps to explore the effect of these two quantities on performance of CMOS digital circuits. The trade-offs between the choice of supply voltage, threshold voltage, device dimensions, delay performance, activity rate, and power consumption are analytically examined using predictive device models, for different technology nodes. Taking into account the circuit reliability requirements, this analysis can be used to optimize the system performance with proper device sizing and selecting supply voltage.