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Laboratoire de circuits pour télécommunications
LaboratoirePublications associées (1 000)
Integrated Wireless Power, Data Communication, and Thermal Sensing System for Autonomous Multisite Brain Implants
Implanted medical devices (IMDs) have been widely developed to support the monitoring and recording of biological data inside the body or brain. Wirelessly powered IMDs, a subset of implantable electronics, have been proposed to eliminate the limitations r ...
EPFL2024EdgeAI-Aware Design of In-Memory Computing Architectures
Driven by the demand for real-time processing and the need to minimize latency in AI algorithms, edge computing has experienced remarkable progress. Decision-making AI applications stand out for their heavy reliance on data-centric operations, predominantl ...
EPFL2024Contemporary Logic Synthesis: with an Application to AQFP Circuit Optimization
Electronic devices play an irreplaceable role in our lives. With the tightening time to market, exploding demand for computing power, and continuous desire for smaller, faster, less energy-consuming, and lower-cost chips, computer-aided design for electron ...
EPFL2024Highly Parallel RTL Simulation
Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL.As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and s ...
EPFL2024On Speed and Advantage : Results in Information Velocity and Monitoring Problems
Information theory has allowed us to determine the fundamental limit of various communication and algorithmic problems, e.g., the channel coding problem, the compression problem, and the hypothesis testing problem. In this work, we revisit the assumptions ...
EPFL2024A Generalized Adjusted Min-Sum Decoder for 5G LDPC Codes: Algorithm and Implementation
Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Yifei Shen, Yuqing Ren, Hassan Harb
5G New Radio (NR) has stringent demands on both performance and complexity for the design of low-density parity-check (LDPC) decoding algorithms and corresponding VLSI implementations. Furthermore, decoders must fully support the wide range of all 5G NR bl ...
Ieee-Inst Electrical Electronics Engineers Inc2024Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism
Adam Shmuel Teman, Robert Giterman
Embedded memories occupy an increasingly dominant part of the area and power budgets of modern systems-on-chips (SoCs). Multi-ported embedded memories, commonly used by media SoCs and graphical processing units, occupy even more area and consume higher pow ...
MDPI2024High-Throughput and Flexible Belief Propagation List Decoder for Polar Codes
Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Andreas Toftegaard Kristensen, Yifei Shen, Yuqing Ren, Chuan Zhang
Due to its high parallelism, belief propagation (BP)decoding is amenable to high-throughput applications and thusrepresents a promising solution for the ultra-high peak datarate required by future communication systems. To bridge theperformance gap compare ...
Ieee-Inst Electrical Electronics Engineers Inc2024Accelerator-driven Data Arrangement to Minimize Transformers Run-time on Multi-core Architectures
David Atienza Alonso, Giovanni Ansaloni, Alireza Amirshahi
The increasing complexity of transformer models in artificial intelligence expands their computational costs, memory usage, and energy consumption. Hardware acceleration tackles the ensuing challenges by designing processors and accelerators tailored for t ...
2024DBFS: Dynamic Bitwidth-Frequency Scaling for Efficient Software-defined SIMD
Giovanni Ansaloni, Alexandre Sébastien Julien Levisse, Pengbo Yu, Flavio Ponzina
Machine learning algorithms such as Convolutional Neural Networks (CNNs) are characterized by high robustness towards quantization, supporting small-bitwidth fixed-point arithmetic at inference time with little to no degradation in accuracy. In turn, small ...
2024