DRAM Based on Hysteresis in Impact Ionization Single-Transistor-Latch

This work reports on memory applications of punch-through impact ionization single-transistor latch (PIMOS), showing abrupt current switching (3-10mV/dec.) as well as hysteresis in both ID(VDS) and ID(VGS). A capacitor-less 1PIMOS - 1 MOSFET DRAM memory is proposed, to exploit the hysteretic PIMOS characteristic and reduce the power consumption, and experimentally validated. A fundamental problem for CMOS technology is the 60 mV/dec. room temperature limit in the subthreshold slope, which is further aggravated by scaling and reduced bias voltages. This has spurred the interest in alternative architectures for small slope switches exploiting gate controlled nonlinearity of the device, such as the impact ionization FET, IMOS. We have previously reported on the abrupt switching combined with hysteresis in the ID(VDS) and ID(VGS) in Ω-gate MOSFETs operating in punch-through. In this work the use of such punch-through impact ionization MOSFET (PIMOS) for a capacitor-less DRAM is proposed. The PIMOS structure corresponds to that of a MOSFET, unlike an IMOS which is a gated p-i-n diode. The devices are fabricated on a bulk silicon platform using standard microelectronic processes, enabling an Ω- or tri-gate cross-section. The devices operate as short-channel devices, due to the low doping of the substrate; required to achieve the essential condition of punch-through. Physical device length is 1.4μm, width varies from 2 to 40μm and gate oxide thickness is 10nm. For low drain voltages the device operates as a MOSFET. When biased in subthreshold a high VDS (~8V) causes impact ionization and avalanching at the drain side of the channel. This mechanism is responsible for the abrupt transition slope, ranging from 3-10mV/dec. The hysteresis is maintained by the turn-on of a parasitic BJT, when the source-substrate junction becomes forward biased. By biasing VDS within the hysteresis loop it is possible to reproduce the hysteresis in the ID(VGS) characteristics. Both the hysteresis in ID(VDS) and ID(VGS) have a height of about two decades in current and span 1-2V in width. A capacitor-less DRAM architecture is proposed, based on the ID(VDS) hysteresis. In addition to the PIMOS acting as a capacitor-less storage cell an access transistor is used acting as a common gate topology and decupling the drain voltage of the PIMOS to shut-off the leakage current in the off state. The memory state is read through the ID of the PIMOS storage transistor. The gate of the access transistor is driven by a multi-level voltage that is used to set the voltage level of the PIMOS to write, read and address the memory cell. The output data is obtained by a current comparison at the bit line node (BL) with a reference current. This architecture has the advantage of shutting off current during hold, thus reducing power consumption. After operation of the PI-MOS for more than 10.000 cycles the hysteresis loop is maintained, confirming that no hot carrier degradation takes place.