Publication
This paper investigates and models Gate Induced Drain Leakage (GIDL) for a wide variety of high voltage devices with different low doped drain (LDD) structures. Based on TCAD simulations, we propose semi-analytical a pseudo-2D model for Gate induced Drain leakage. This model includes a complete modeling of the overlap region accounting for technological process and bulk bias dependency through detailed electric field description.
Elison de Nazareth Matioli, Luca Nela, Taifang Wang
Elison de Nazareth Matioli, Luca Nela, Catherine Erine