Publication
Tunable floating active inductor with internal offset reduction
Abstract
Presented is a transistor-level implementation of a floating and tunable CMOS active inductor. It is based on the classical gyrator-C topology and is enhanced by adding an internal offset reduction mechanism to guarantee functionality also for unbalanced DC conditions. The realised inductance can be programmed for values between 685 mu H and 12.4 mH and is designed to be implemented using standard CMOS technology. Its range of operation is from 250 to 750 kHz and the inductor consumption does not exceed 2 mW.
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