Silicon CMOS and InGaAs(P)/InP SPADs for NIR/SWIR detection

Applications demanding imaging at low-light conditions at near-infrared (NIR) and short-wave infrared (SWIR) wavelengths, such as quantum information science, biophotonics, space imaging, and light detection and ranging (LiDAR), have accelerated the development of NIR/SWIR single-photon detectors. Up to date, there have been various detector types performing single-photon detection at infrared wavelengths. Among them, single-photon avalanche diodes (SPADs) have gained significant attention thanks to their low noise near room temperature (< 100 cps), high detection efficiencies (> 50%), and low timing jitter (< 100 ps). In addition, the integration of SPADs with standard CMOS technologies has paved the way for the design of low-cost, large pixel arrays with embedded photon-counting and timestamping circuitry. For detection at NIR/SWIR, Si CMOS and InGaAs(P)/InP-based SPADs appear as the most promising material systems. Si CMOS has the advantage of yielding low noise and integrating SPADs with on-chip readout circuits; however, the low absorption coefficient towards NIR is a bottleneck to enhancing detection efficiencies. In this sense, the wide depletion region approach was investigated in this work by designing SPADs in a 110 nm CIS technology with a 10 um active diameter. The implemented techniques of doping compensation and double multiplication region showed that the former can be utilized to extend depletion region widths, whereas the latter increases the total avalanche breakdown probability in a wide depletion SPAD, leading to high NIR efficiencies at a relatively lower breakdown voltage. In the fabricated SPADs with doping compensation, 7.3% PDP and 68 ps timing jitter at 850 nm and 5 Vex were achieved under the noise of 962 cps. Thanks to a fully substrate-non-isolated structure with graded substrate doping and enhanced breakdown probabilities, 25.5% PDP at 850 nm and 5.5 Vex were obtained in the device with the double multiplication region with a 295 cps noise, all at room temperature. However, the jitter at 850 nm was deteriorated to 236 ps due to many detected diffused carriers creating a diffusion peak in the timing histogram. InGaAs(P)/InP-based SPADs were also designed, fabricated, and characterized, targeting 1.06 um and 1.55 um wavelengths. Planar device structures based on double zinc diffusions were implemented to define the active and guard ring regions of the SPADs. A comprehensive study was conducted via TCAD simulations to adjust the multiplication region thickness and the depth difference between two diffusions, which allowed for optimization of noise and active area uniformity. The numerical study also enabled the removal of floating guard rings, shrinking pixel sizes for future array implementation. The noise of a 10 um device with an InGaAsP absorber and a 1.5 um multiplication region at 5 Vex was 14.1 kcps, 5.5 kcps, and 2.75 kcps at 273K, 253K, and 225K, respectively, at 10 kHz frequency and 100 ns gate-on time. It was shown that the maximum operating frequency can be increased up to 200 kHz without suffering from the afterpulsing effect near room temperature. The PDP can be increased up to 36% at 9 Vex and 1060 nm wavelength, and the jitter was reduced to 118.4 ps at 5 Vex and 1060 nm. A 10 um SPAD with an InGaAs absorber and 1.5 um multiplication region achieved 20% PDP at 1550 nm and 61 kcps noise, both at 6 Vex. The jitter of this device was 123 ps at 1550 nm and 5 Vex.