Publications related to Logic synthesis

Technology-Aware Logic Synthesis for Superconducting Electronics

Giovanni De Micheli, Alessandro Tempia Calvino, Dewmini Sudara Marakkalage, Mingfei Yu, Siang-Yun Lee, Rassul Bairamkulov

Superconducting electronics provide us with cryogenic digital circuits that can rival established technologies in performance and energy consumption. Today, the lack of tools for the design of large-scale integrated superconducting circuits is a major obst ...

2024

Algebraic and Boolean Methods for SFQ Superconducting Circuits

Giovanni De Micheli, Alessandro Tempia Calvino

Rapid single-flux quantum (RSFQ) is one of the most advanced and promising superconducting logic families, offering exceptional energy efficiency and speed. RSFQ technology requires delay registers (DFFs) and splitter cells to satisfy the path-balancing an ...

2024

Scalable Logic Rewriting Using Don’t Cares

Giovanni De Micheli, Alessandro Tempia Calvino

Logic rewriting is a powerful optimization technique that replaces small sections of a Boolean network with better implementations. Typically, exact synthesis is used to compute optimum replacement on-the-fly, with possible support for Boolean don't cares. ...

2024

Strain relaxation and multidentate anchoring in n-type perovskite transistors and logic circuits

Mohammad Khaja Nazeeruddin, Olga Syzgantseva

The engineering of tin halide perovskites has led to the development of p-type transistors with field-effect mobilities of over 70 cm2 V-1 s-1. However, due to their background hole doping, these perovskites are not suitable for n-type transistors. Ambipol ...

Nature Portfolio2024

Technology Mapping Using Multi-output Library Cells

Giovanni De Micheli, Alessandro Tempia Calvino

Technology mapping transforms a technology-independent representation into a technology-dependent one given a library of cells. Even if technology libraries contain multi-output cells, state-of-the-art techniques fully exploit single-output cells only. Mul ...

2023

Resource Sharing in Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic, Axel Marmet

To achieve resource-efficient hardware designs, high-level synthesis (HLS) tools share (i.e., time-multiplex) functional units among operations of the same type. This optimization is typically performed in conjunction with operation scheduling to ensure th ...

New York2023

IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck

Mirjana Stojilovic, Stefan Nikolic, Shashwat Shrivastava

We identified that in modern commercial FPGAs, routing signals from the general interconnect to the configurable logic blocks (CLBs) through a very sparse input interconnect block (IIB) represents a significant runtime bottleneck. This is despite academic ...

2023

Unraveling the Electrochemical Electrode Coupling in Integrated Organic Electrochemical Transistors

Matteo Cucchi, Hsin Tseng

Organic electrochemical transistors (OECTs) have gained enormous attention due to their potential for bioelectronics and neuromorphic computing. However, their implementation into real-world applications is still impeded by a lack of understanding of the c ...

WILEY-V C H VERLAG GMBH2023

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Logic synthesis

Contemporary Logic Synthesis: with an Application to AQFP Circuit Optimization

Technology-Aware Logic Synthesis for Superconducting Electronics

Algebraic and Boolean Methods for SFQ Superconducting Circuits

Scalable Logic Rewriting Using Don’t Cares

Strain relaxation and multidentate anchoring in n-type perovskite transistors and logic circuits

Technology Mapping Using Multi-output Library Cells

Resource Sharing in Dataflow Circuits

IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck

Evaluating, Exploiting, and Hiding Power Side-Channel Leakage of Remote FPGAs

Unraveling the Electrochemical Electrode Coupling in Integrated Organic Electrochemical Transistors

Graph Chatbot

Chat with Graph Search

Contemporary Logic Synthesis: with an Application to AQFP Circuit Optimization

Technology Mapping Using Multi-output Library Cells

Scalable Logic Rewriting Using Don’t Cares

Resource Sharing in Dataflow Circuits

Unraveling the Electrochemical Electrode Coupling in Integrated Organic Electrochemical Transistors

IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck

Algebraic and Boolean Methods for SFQ Superconducting Circuits

Technology-Aware Logic Synthesis for Superconducting Electronics

Strain relaxation and multidentate anchoring in n-type perovskite transistors and logic circuits

Evaluating, Exploiting, and Hiding Power Side-Channel Leakage of Remote FPGAs