65 nm process

The 65 nm process is an advanced lithographic node used in volume CMOS (MOSFET) semiconductor fabrication. Printed linewidths (i.e. transistor gate lengths) can reach as low as 25 nm on a nominally 65 nm process, while the pitch between two lines may be greater than 130 nm. For comparison, cellular ribosomes are about 20 nm end-to-end. A crystal of bulk silicon has a lattice constant of 0.543 nm, so such transistors are on the order of 100 atoms across. By September 2007, Intel, AMD, IBM, UMC and Chartered were also producing 65 nm chips. While feature sizes may be drawn as 65 nm or less, the wavelengths of light used for lithography are 193 nm and 248 nm. Fabrication of sub-wavelength features requires special imaging technologies, such as optical proximity correction and phase-shifting masks. The cost of these techniques adds substantially to the cost of manufacturing sub-wavelength semiconductor products, with the cost increasing exponentially with each advancing technology node. Furthermore, these costs are multiplied by an increasing number of mask layers that must be printed at the minimum pitch, and the reduction in yield from printing so many layers at the cutting edge of the technology. For new integrated-circuit designs, this factors into the costs of prototyping and production. Gate thickness, another important dimension, is reduced to as little as 1.2 nm (Intel). Only a few atoms insulate the "switch" part of the transistor, causing charge to flow through it. This undesired leakage is caused by quantum tunneling. The new chemistry of high-κ gate dielectrics must be combined with existing techniques, including substrate bias and multiple threshold voltages, to prevent leakage from prohibitively consuming power. IEDM papers from Intel in 2002, 2004, and 2005 illustrate the industry trend that the transistor sizes can no longer scale along with the rest of the feature dimensions (gate width only changed from 220 nm to 210 nm going from 90 nm to 65 nm technologies).

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65 nm process

An All-Digital 1 Mbps, 57 pJ/bit Bluetooth Low Energy (BLE) Backscatter ASIC in 65 nm CMOS

James Daniel Rosenthal

We present an all-digital application specific integrated circuit (ASIC) that implements Bluetooth Low Energy (BLE)-compatible backscatter communication. The ASIC was fabricated in a 65 nm CMOS process and occupies an active area of 0.12 mm(2) while consuming a total of 205 mu W DC power from 0.48 V and 1 V supplies. Of the total power consumption, 56% (115 mu W) is consumed by the digital logic, 16% (33 mu W) by the on-chip clock oscillator, and 28% (57 mu W) by the RF switch used as a backscatter modulator. The ASIC broadcasts up to 1000 BLE advertising packets per second at a data rate of 1 Mbps, yielding a backscatter modulator efficiency of 57 pJ/bit. The device was validated in both cabled and wireless (over-the-air) measurement setups, demonstrating compatibility with unmodified smartphones as well as commercially available BLE chips, such as the Nordic Semiconductor nRF51822. With the wireless test setup used in this work, and assuming a +10 dBm carrier source, the ASIC has a theoretical maximum read range of 4.9 m using a smartphone as the receiver. Building from previous work in BLE backscatter communication using FPGA-based prototypes, this work provides an important quantitative demonstration of the size and power savings that can be achieved in a BLE-compatible backscatter ASIC.

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