Publications related to OR gate

Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù, Sandeep Miryala

As an answer to the new electronics market demands, semiconductor industry is looking for different materials, new process technologies and alternative design solutions that can support Silicon replacement in the VLSI domain. The recent introduction of gra ...

ACM2015

A Survey on Low-Power Techniques with Emerging Technologies: From Devices to Systems

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon

Nowadays, power consumption is one of the main limitations of electronic systems. In this context, novel and emerging devices provide us with new opportunities to keep the trend to low-power design. In this survey paper, we present a transversal survey on ...

Assoc Computing Machinery2015

Improved carry chain mapping for the VTR flow

Paolo Ienne, Grace Zgheib, David Novo Bruna, Ana Petkovska

Carry chains facilitate the implementation of adders and improve the performance of arithmetic circuits in FPGAs. The last version of the commonly used open-source Verilog-to-Routing (VTR) CAD flow now enables modelling carry chains in FPGA architectures. ...

IEEE2015

On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors

Giovanni De Micheli, Eduardo Sanchez, Pierre-Emmanuel Julien Marc Gaillardon, Jian Zhang, Hassan Ghasemzadeh Mohammadi

This paper first explores the effects of faults on circuits implemented with controllable-polarity transistors. We propose a new fault model that suits the characteristics of these devices, and report the results of a SPICE-based analysis of the effects of ...

IEEE2015

Multiple Independent Gate FETs: How Many Gates Do We Need?

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù, Subhasish Mitra

Multiple Independent Gate Field Effect Transistors (MIGFETs) are expected to push FET technology further into the semiconductor roadmap. In a MIGFET, supplementary gates either provide (i) enhanced conduction properties or (ii) more intelligent sw ...

IEEE2015

Role of the gate in ballistic nanowire SOI MOSFETs

Christian Enz, Jean-Michel Sallese, Anurag Mangla

In this paper we report the results of Monte-Carlo simulations performed on double-gate ballistic MOSFETs with a geometry such that the gates overlap only a fraction of the channel. We present a qualitative analysis of the simulation results highlighting t ...

Elsevier2015

Impact of Asymmetric Configurations on the Heterogate Germanium Electron-Hole Bilayer Tunnel Field-Effect Transistor Including Quantum Confinement

Mihai Adrian Ionescu, Cem Alper, José Luis Padilla de la Torre

We investigate the effect of asymmetric configurations on the heterogate germanium electron-hole bilayer tunnel field-effect transistor (HG-EHBTFET) and assess the improvement that they provide in terms of boosting the typically very low ON current levels ...

Institute of Electrical and Electronics Engineers2015

Automatic Generation of Inexact Digital Circuits by Gate-level Pruning

Christian Enz, Vincent Frédéric Camus, Jérémy Lucien Maurice Schlachter

Inexact or approximate circuits show great ability to reduce power consumption at the cost of occasional errors in comparison to their conventional counterparts. Even though the benefits of such circuits have been proven for many applications, they are not ...

2015

Self-biased reconfigurable graphene stacks for terahertz plasmonics

Mihai Adrian Ionescu, Arnaud Magrez, Clara-Fausta Moldovan, Julien Perruisseau-Carrier, Santiago Capdevila Cascante, Laurent Syavoch Bernard

The gate-controllable complex conductivity of graphene offers unprecedented opportunities for reconfigurable plasmonics at terahertz and mid-infrared frequencies. However, the requirement of a gating electrode close to graphene and the single 'control knob ...

Nature Publishing Group2015

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OR gate

Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization

A Survey on Low-Power Techniques with Emerging Technologies: From Devices to Systems

Improved carry chain mapping for the VTR flow

On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors

Multiple Independent Gate FETs: How Many Gates Do We Need?

Role of the gate in ballistic nanowire SOI MOSFETs

Impact of Asymmetric Configurations on the Heterogate Germanium Electron-Hole Bilayer Tunnel Field-Effect Transistor Including Quantum Confinement

Polarity Control at Runtime

Automatic Generation of Inexact Digital Circuits by Gate-level Pruning

Self-biased reconfigurable graphene stacks for terahertz plasmonics

Graph Chatbot

Chat with Graph Search

Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization

Improved carry chain mapping for the VTR flow

Impact of Asymmetric Configurations on the Heterogate Germanium Electron-Hole Bilayer Tunnel Field-Effect Transistor Including Quantum Confinement

A Survey on Low-Power Techniques with Emerging Technologies: From Devices to Systems

Multiple Independent Gate FETs: How Many Gates Do We Need?

On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors

Polarity Control at Runtime

Role of the gate in ballistic nanowire SOI MOSFETs

Self-biased reconfigurable graphene stacks for terahertz plasmonics

Automatic Generation of Inexact Digital Circuits by Gate-level Pruning