Concept

Peripheral Component Interconnect

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Peripheral Component Interconnect

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High Performance Transaction Processing on Non-Uniform Hardware Topologies

Cost-Effective Design of Mesh-of-Tree Interconnect for Multi-Core Clusters with 3-D Stacked L2 Scratchpad Memory

Caching (a pair of) Gaussians

Acquisition of modern GNSS signals using a modified parallel code-phase search architecture

An Enhanced Design Methodology for Resonant Clock Trees

Scale-Out Processors

3D-LIN: A Configurable Low-Latency Interconnect for Multi-Core Clusters with 3D Stacked L1 Memory

Scale-Out Processors

Low-power clock distribution networks for 3-D ICs

Design of Resonant Clock Distribution Networks for 3-D Integrated Circuits

High Performance Transaction Processing on Non-Uniform Hardware Topologies

Caching (a pair of) Gaussians

Low-power clock distribution networks for 3-D ICs

Scale-Out Processors

Design of Resonant Clock Distribution Networks for 3-D Integrated Circuits

Cost-Effective Design of Mesh-of-Tree Interconnect for Multi-Core Clusters with 3-D Stacked L2 Scratchpad Memory

Acquisition of modern GNSS signals using a modified parallel code-phase search architecture

3D-LIN: A Configurable Low-Latency Interconnect for Multi-Core Clusters with 3D Stacked L1 Memory

An Enhanced Design Methodology for Resonant Clock Trees

Scale-Out Processors