Publications related to Peripheral Component Interconnect

IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck

Mirjana Stojilovic, Stefan Nikolic, Shashwat Shrivastava

We identified that in modern commercial FPGAs, routing signals from the general interconnect to the configurable logic blocks (CLBs) through a very sparse input interconnect block (IIB) represents a significant runtime bottleneck. This is despite academic ...

2023

A 500 x 500 Dual-Gate SPAD Imager With 100% Temporal Aperture and 1 ns Minimum Gate Length for FLIM and Phasor Imaging Applications

Edoardo Charbon, Claudio Bruschini, Andrei Ardelean, Paul Mos, Arin Can Ülkü, Michael Alan Wayne

In this article, we report on SwissSPAD3 (SS3), a 500 x 500 pixel single-photon avalanche diode (SPAD) array, fabricated in 0.18-mu m CMOS technology. In this sensor, we introduce a novel dual-gate architecture with two contiguous temporal windows, or gate ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Modeling and optimization of dedicated bus lanes space allocation in large networks with dynamic congestion

Nikolaos Geroliminis, Dimitrios Tsitsokas, Anastasios Kouvelas

Dedicated bus lanes provide a low cost and easily implementable strategy to improve transit service by minimizing congestion-related delays. Identifying the best spatial distribution of bus-only lanes in order to maximize traffic performance of an urban ne ...

2021

Evading Voltage-Based Intrusion Detection on Automotive CAN

Mathias Josef Payer, Duo Xu, Rohit Bhatia

The controller area network (CAN) is widely adopted in modern automobiles to enable communications among in-vehicle electronic control units (ECUs). Lacking mainstream network security capabilities due to resource constraints, the CAN is susceptible to the ...

INTERNET SOC2021

GPU-accelerated data management under the test of time

Anastasia Ailamaki, Periklis Chrysogelos, Angelos Christos Anadiotis, Panagiotis Sioulas, Syed Mohammad Aunn Raza

GPUs are becoming increasingly popular in large scale data center installations due to their strong, embarrassingly parallel, processing capabilities. Data management systems are riding the wave by using GPUs to accelerate query execution, mainly for analy ...

2020

An Eight lanes 7Gb/s/pin Source Synchronous Single-Ended RX with Equalization and Far-End Crosstalk Cancellation for Backplane Channels

Volkan Cevher, Cosimo Aprile, Yusuf Leblebici, Alessandro Cevrero, Lukas Kull, Thomas Toifl

This paper presents a versatile crosstalk cancellation scheme for single-ended multi-lane backplane links. System-level investigations show that a scheme, which combines analog filters and decision-feedback crosstalk compensation on the receiver (RX) side ...

2018

Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes

Andreas Peter Burg, Adam Shmuel Teman, Andrea Bonetti, Nicholas Alexander Preyss

Clocking power, including both clock distribution and registers, has long been one of the primary factors in the total power consumption of many digital systems. One straightforward approach to reduce this power consumption is to apply dual-edge-triggered ...

Association for Computing Machinery2017

A Power-Efficient 3-D On-Chip Interconnect for Multi-Core Accelerators with Stacked L2 Cache

Giovanni De Micheli, Luca Benini

The use of multi-core clusters is a promising option for data-intensive embedded applications such as multi-modal sensor fusion, image understanding, mobile augmented reality. In this paper, we propose a power-efficient 3-D on-chip interconnect for multi-c ...

IEEE2016

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Peripheral Component Interconnect

IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck

A 500 x 500 Dual-Gate SPAD Imager With 100% Temporal Aperture and 1 ns Minimum Gate Length for FLIM and Phasor Imaging Applications

Uncooperative Rendezvous in Space: Design of an Electronic Architecture for High Performance Avionic with Multi Sensor Input and Intensive Data Rate.

Modeling and optimization of dedicated bus lanes space allocation in large networks with dynamic congestion

Evading Voltage-Based Intrusion Detection on Automotive CAN

Shining Diamond: from Micro- and Nano-Engineering to Quantum Photonics

GPU-accelerated data management under the test of time

An Eight lanes 7Gb/s/pin Source Synchronous Single-Ended RX with Equalization and Far-End Crosstalk Cancellation for Backplane Channels

Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes

A Power-Efficient 3-D On-Chip Interconnect for Multi-Core Accelerators with Stacked L2 Cache

Graph Chatbot

Chat with Graph Search

IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck

A 500 x 500 Dual-Gate SPAD Imager With 100% Temporal Aperture and 1 ns Minimum Gate Length for FLIM and Phasor Imaging Applications

Modeling and optimization of dedicated bus lanes space allocation in large networks with dynamic congestion

Evading Voltage-Based Intrusion Detection on Automotive CAN

Shining Diamond: from Micro- and Nano-Engineering to Quantum Photonics

Uncooperative Rendezvous in Space: Design of an Electronic Architecture for High Performance Avionic with Multi Sensor Input and Intensive Data Rate.

GPU-accelerated data management under the test of time

Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes

An Eight lanes 7Gb/s/pin Source Synchronous Single-Ended RX with Equalization and Far-End Crosstalk Cancellation for Backplane Channels

A Power-Efficient 3-D On-Chip Interconnect for Multi-Core Accelerators with Stacked L2 Cache