Concept

NAND gate

Related publications (108)

Oscillator Based on Suspended Gate MOS Transistors

Mihai Adrian Ionescu, Marco Mazza, Yogesh Singh Chauhan, Alexandru Rusu

The paper deals with the oscillator applications based on vibrating mode of the suspended gate SG-MOSFET transistor. In order to simulate the electrical behavior of the transistor a small-signal equivalent circuit of the gate is proposed and validated. An ...

2008

Prospects for logic-on-a-wire

Giovanni De Micheli, Mihai Adrian Ionescu, David Atienza Alonso, Didier Bouvet, Kirsten Emilie Moselund, Yusuf Leblebici, Mohamed Haykel Ben Jamaa

In this paper we present the top-down fabrication of gate-all-around (GAA) and body-tied @W-gate devices by a combination of etching and oxidation steps resulting in a local silicon-on-insulator structure. The GAA has advantages in terms of enhanced curren ...

2008

Impact of Lateral Asymmetry of MOSFETs on the Gate and Drain Noise Correlation

Christian Enz, Ananda Sankar Roy

Recent studies of Lim et al. have shown that channel engineering can effectively be used to globally improve the device noise performance. This happens because the doping profile can strongly impact the correlation between the drain and induc ...

2008

Abrupt NMOS Inverter Based on Punch-Through Impact Ionization With Hysteresis in the Voltage Transfer Characteristics

Mihai Adrian Ionescu, Didier Bouvet, Kirsten Emilie Moselund

In this letter, an abrupt NMOS inverter based on punch-through impact ionization is demonstrated for the first time. The slopes for both the rising and the falling edge of the ID(V GS) device characteristics are less than 10 mV/dec ...

2008

Fabrication and Characterization of Gate-All-Around Silicon Nanowires on Bulk Silicon

Mihai Adrian Ionescu, Didier Bouvet, Kirsten Emilie Moselund, Vincent Pott, Luca De Michielis

This paper reports on the top-down fabrication and electrical performance of silicon nanowire (SiNW) gate-all-around (GAA) n-type and p-type MOSFET devices integrated on bulk silicon using a local-silicon-on-insulator (SOI) process. The proposed local-SOI ...

2008

Fault-Tolerant Logic Gates Using Neuromorphic CMOS Circuits

Alexandre Schmid, Yusuf Leblebici, Neil Joye

Fault-tolerant design methods for VLSI circuits, which have traditionally been addressed at system level, will not be adequate for future very-deep submicron CMOS devices where serious degradation of reliability is expected. Therefore, a new design approac ...

IEEE2007

Fabrication of silicon nano wires and gate-all-around MOS devices

Didier Bouvet, Kirsten Emilie Moselund

The invention relates to methods for manufacturing semiconductor devices. Processes are disclosed for implementing suspended single crystal silicon nano wires (NWs) using a combination of anisotropic and isotropic etches and spacer creation for sidewall pr ...

2007

Gate-lag and drain-lag effects in (GaN)/InAlN/GaN and InAlN/AlN/GaN HEMTs

Nicolas Grandjean, Jean-François Carlin, Marcus Gonschorek

Gate and drain-lag effects are studied in (GaN)/InAlN/GaN and InAlN/AlN/GaN HEMTs grown on sapphire. Electron trapping on the surface states between the gate and the drain forming the net negative charge up-to similar to 2 x 10(13) cm(-2) is found to be re ...

2007

Étude du tomographe de haute résolution pour petits animaux ClearPET par la méthode de Monte Carlo

Martin Rey

The Lausanne ClearPET demonstrator is one of the new generation of high resolution small animal PET scanners. A high resolution PET scanner aims to maximize the signal-to-noise ratio measured in pixels for a given time without compromising spatial resoluti ...

EPFL2007

Gate-all-around silicon nanowires for hybrid single electron transistor/CMOS applications

Vincent Pott

Scaling of semiconductor devices has pushed CMOS devices close to fundamental limits. The remarkable success story of Moore's law during the last 40 years, predicting the evolution of electronic device performances related to miniaturization, has always be ...

EPFL2007

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