Concept

Invention of the integrated circuit

Related publications (41)

Controlling On-Surface Photoactivity: The Impact of π-Conjugation in Anhydride-Functionalized Molecules on a Semiconductor Surface

On-surface synthesis has become a prominent method for growing low-dimensional carbon-based nanomaterials on metal surfaces. However, the necessity of decoupling organic nanostructures from metal substrates to exploit their properties requires either trans ...

Wiley-V C H Verlag Gmbh2024

Towards Scalable Electronics: Synthetic 2D Materials for Large-Area 2D Circuit Integration

Zhenyu Wang

In the past decades, a significant increase of the transistor density on a chip has led to exponential growth in computational power driven by Moore's law. To overcome the bottleneck of traditional von-Neumann architecture in computational efficiency, effo ...

EPFL2024

Edge-Contact MoS2 Transistors Fabricated Using Thermal Scanning Probe Lithography

Jürgen Brugger, Giovanni Boero, Xia Liu, Ana Conde Rubio

The science and engineering of two-dimensional materials (2DMs), in particular, of 2D semiconductors, is advancing at a thriving pace. It is well known that these delicate few-atoms thick materials can be damaged during the processing toward their integrat ...

AMER CHEMICAL SOC2022

A cryo-CMOS chip that integrates silicon quantum dots and multiplexed dispersive readout electronics

Edoardo Charbon, Andrea Ruffino, Yatao Peng

An integrated circuit fabricated using industry-standard 40 nm complementary metal-oxide-semiconductor technology can combine silicon quantum devices, digital addressing and analogue multiplexed dispersive readout electronics. As quantum computers grow in ...

NATURE PORTFOLIO2021

ANTIGONE: A Programmable Energy-Efficient Current Digitizer for an ISFET Wearable Sweat Sensing System

Maher Kayal, Evgenia Voulgari, François Krummenacher

This article describes the design and the characterization of the ANTIGONE (ANalog To dIGital cONvErter) ASIC (Application Specific Integrated Circuit) built in AMS 0.35 m technology for low dc-current sensing. This energy-efficient ASIC was specifically d ...

2021

WSe2/SnSe2 vdW heterojunction Tunnel FET with subthermionic characteristic and MOSFET co-integrated on same WSe2 flake

Mihai Adrian Ionescu, Matteo Cavalieri, Nicolò Oliva, Luca Capua

Two-dimensional/two-dimensional (2D/2D) heterojunctions form one of the most versatile technological solutions for building tunneling field effect transistors because of the sharp and potentially clean interfaces resulting from van der Waals assembly. Seve ...

NATURE PUBLISHING GROUP2020

Reduction of Fermi level pinning at Cu-BP interfaces by atomic passivation

Xiao Zhou, Cheng Chen, Pengfei Ou

Black phosphorus (BP) is a semiconducting material with a direct finite band gap in its monolayer, attracting intense attention for its application in field-effect transistors. However, strong Fermi level pinning (FLP) has been observed for contacts betwee ...

2019

Tri-gate technologies for high-performance power GaN devices

Jun Ma

GaN-based electronic devices have great potential for future power applications, thanks to their wide band-gap, high breakdown electric field, and high electron mobility. In addition, these devices can be integrated on large-size Si substrates and enable n ...

EPFL2019

Interdigitated back contact silicon heterojunction solar cells featuring an interband tunnel junction enabling simplified processing

Christophe Ballif, Quentin Thomas Jeangros, Antoine Descoeudres, Antonin Faes, Gabriel Christmann, Bertrand Yves Paul Paviet-Salomon, Jonas Geissbühler, Nicolas Badel, Matthieu Despeisse, Stefaan De Wolf, Sylvain Nicolay, Loris Barraud, Benjamin Strahm, Johannes Peter Seif, Andrea Tomasi

This paper reports on the development of an innovative back-contacted crystalline silicon solar cell with passivating contacts featuring an interband tunnel junction at its electron-collecting contacts. In this novel architecture, named "tunnel-IBC", both ...

2018

A High-PDE, Backside-Illuminated SPAD in 65/40-nm 3D IC CMOS Pixel With Cascoded Passive Quenching and Active Recharge

Edoardo Charbon, Scott Anthony Lindner, Martin Wolf

We present a complete pixel based on a single-photon avalanche diode (SPAD) fabricated in a backside-illuminated (BSI) 3D IC technology. The chip stack comprises an image sensing tier produced in a 65-nm image sensor technology and a data processing tier i ...

2017

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