In electronics and telecommunications, jitter is the deviation from true periodicity of a presumably periodic signal, often in relation to a reference clock signal. In clock recovery applications it is called timing jitter. Jitter is a significant, and usually undesired, factor in the design of almost all communications links.
Jitter can be quantified in the same terms as all time-varying signals, e.g., root mean square (RMS), or peak-to-peak displacement. Also, like other time-varying signals, jitter can be expressed in terms of spectral density.
Jitter period is the interval between two times of maximum effect (or minimum effect) of a signal characteristic that varies regularly with time. Jitter frequency, the more commonly quoted figure, is its inverse. ITU-T G.810 classifies deviation lower frequencies below 10 Hz as wander and higher frequencies at or above 10 Hz as jitter.
Jitter may be caused by electromagnetic interference and crosstalk with carriers of other signals. Jitter can cause a display monitor to flicker, affect the performance of processors in personal computers, introduce clicks or other undesired effects in audio signals, and cause loss of transmitted data between network devices. The amount of tolerable jitter depends on the affected application.
For clock jitter, there are three commonly used metrics:
Absolute jitter
The absolute difference in the position of a clock's edge from where it would ideally be.
Maximum time interval error (MTIE)
Maximum error committed by a clock under test in measuring a time interval for a given period of time.
Period jitter (a.k.a. cycle jitter)
The difference between any one clock period and the ideal or average clock period. Period jitter tends to be important in synchronous circuitry such as digital state machines where the error-free operation of the circuitry is limited by the shortest possible clock period (average period less maximum cycle jitter), and the performance of the circuitry is set by the average clock period.
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The course is covering following aspects: Fundamentals of Analog PLLs, Interference Effects, Deadzone and Phase Noise, VCO Design, All-Digital PLL Architecture and Implementation, Digitally-Controlled
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We introduce a new family of single-photon avalanche diodes (SPADs) with enhanced depletion regions in a 55-nm Bipolar-CMOS-DMOS (BCD) technology. We demonstrate how to systematically engineer doping profiles in the main junction and in deep p-well layers ...
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This article presents a low-jitter and low-spur charge-sampling phase-locked loop (CSPLL). A charge-domain sub-sampling phase detector is introduced to achieve a high phase-detection gain and to reduce the PLL in-band phase noise. Even without employing an ...