Jitter | EPFL Graph Search

In electronics and telecommunications, jitter is the deviation from true periodicity of a presumably periodic signal, often in relation to a reference clock signal. In clock recovery applications it is called timing jitter. Jitter is a significant, and usually undesired, factor in the design of almost all communications links. Jitter can be quantified in the same terms as all time-varying signals, e.g., root mean square (RMS), or peak-to-peak displacement. Also, like other time-varying signals, jitter can be expressed in terms of spectral density. Jitter period is the interval between two times of maximum effect (or minimum effect) of a signal characteristic that varies regularly with time. Jitter frequency, the more commonly quoted figure, is its inverse. ITU-T G.810 classifies deviation lower frequencies below 10 Hz as wander and higher frequencies at or above 10 Hz as jitter. Jitter may be caused by electromagnetic interference and crosstalk with carriers of other s

High Performance InP-Based Quantum Dash Semiconductor Mode-Locked Lasers for Optical Communications

Anthony Martinez

Several applications are pushing the development of high performance mode-locked lasers: generation of short pulses for extremely high bit rate transmission at 100 Gb/s and beyond, all-optical clock recovery at 40 Gb/s and beyond, generation of millimeter wave signals through mode-beating on a high speed photodiode, optical sampling for analog-to-digital conversion, and generation of wavelength-division-multiplexing channels. This paper will report on new advances in InP-based quantum dash mode-locked lasers, which largely surpass the performance of their bulk or quantum well counterparts in terms of the mode-beating spectral purity and the bandwidth of optical spectrum. In particular, we will describe the quantum dash nanostructures used for the mode-locked lasers and the dependence of the mode-locking properties on detailed quantum dash structures. We will demonstrate that these quantum dash lasers can be actively mode-locked, generating sub-picosecond or picosecond pulses at different repetition frequencies with extremely low timing jitter. They can also be used to achieve all-optical clock recovery, with timing jitter compliant with International Telecommunication Union (ITU) standards even for highly degraded input optical signal-to-noise ratio. Finally, we demonstrate that, owing to the very wide and flat optical spectrum and the low relative-intensity noise level of the mode-locked laser, error-free transmission over 50 km single mode fiber has been achieved for eight wavelength division multiplexing ITU channels at 10 Gb/s with a channel spacing of 100 GHz. (C) 2009 Alcatel-Lucent.

2009

Guard-Ring-Free InGaAs/InP Single-Photon Avalanche Diode Based on a Novel One-Step Zn-Diffusion Technique

Claudio Bruschini, Edoardo Charbon, Utku Karaca, Ekin Kizilkan, Myung Jae Lee, Vladimir Pesic

This work presents a novel InGaAs/InP SPAD structure fabricated using a selective area growth (SAG) method. The surface topography of the selectively grown film deposited within the 70 mu m diffusion apertures is used to engineer the Zn diffusion profile to suppress premature edge breakdown. The device achieves a highly uniform active area without the need for shallow diffused guard ring (GR) regions that are inherent in standard InGaAs/InP SPADs. We have obtained 33% and 43% photon detection probability (PDP) at 1550 nm, with 5 V and 7 V excess bias, respectively. These measurements were performed at 300 K and 225 K. The dark count rate (DCR) per unit area at room temperature and at 5 V excess bias is 430 cps/mu m(2) and it decreases to 5 cps/mu m(2) at 225 K. Timing jitter is measured with passive quenching at 1550nm as 149 ps at full-width-at-half-maximum (FWHM), (300 K, 5 V excess bias). The proposed technology is suitable for a number of applications, including optical time-domain reflectometry (OTDR), quantum information, and light detection and ranging (LiDAR).

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Hybrid continuous-discrete-time multi-bit delta-sigma A/D converters with auto-ranging algorithm

Sergio Pesenti

In wireless portable applications, a large part of the signal processing is performed in the digital domain. Digital circuits show many advantages. The power consumption and fabrication costs are low even for high levels of complexity. A well established and highly automated design flow allows one to benefit from the constant progress in CMOS technologies. Moreover, digital circuits offer robust and programmable signal processing means and need no external components. Hence, the trend in consumer electronics is to further reduce the part of analog signal processing in the receiver chain of wireless transceivers. Consequently, analog-to-digital converters with higher resolutions and bandwidths are constantly required. The ultimate goal is the direct digitization of radio frequency signals, where the conversion would be performed immediately after the front-end amplifier. ΔΣ-modulation-based converters have proved to be the most suitable to achieve the required performance. Switched-capacitor implementations have been widely used over the last two decades. However, recent publications and books have shown that continuous-time architectures can achieve the same performance with lower power consumption. Most designs found throughout the literature use a single- or few-bit internal quantizer with a high-order modulation. As a result, in order to achieve the resolutions and bandwidths required today, the sampling frequency must exceed 100MHz. This approach leads to non-negligible power consumption in the clock generation. Moreover, the presence of such fast squared signals is not suitable for a system-on-chip comprising radio frequency receivers. In this thesis we propose a low-power strategy relying on a large number of internal levels rather than on a high sampling frequency or modulation order. Besides, a hybrid continuous-discrete-time approach is used to take advantage of the accuracy of switched-capacitor circuits and the low power consumption of continuous-time implementation. The sensitivity to clock jitter brought about by the continuous-time stage is reduced by the use of a large number of levels. An auto-ranging algorithm is developed in this thesis to overcome the limitation of a large-size quantizer under low-voltage supply. Finally, the strategy is applied to a design example addressing typical specifications for a Bluetooth receiver with direct conversion.

EPFL2007

Hybrid continuous-discrete-time multi-bit delta-sigma A/D converters with auto-ranging algorithm

Sergio Pesenti

EPFL2007