Concept
Jitter
Related publications (48)
Analysis of Dampers in Time-Sensitive Networks With Non-Ideal Clocks
Jean-Yves Le Boudec, Ehsan Mohammadpour
Dampers are devices that reduce delay jitter in the context of time-sensitive networks, by delaying packets for the amount written in packet headers. Jitter reduction is required by some real-time applications; beyond this, dampers have the potential to so ...
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022A Low-Jitter and Low-Spur Charge-Sampling PLL
Edoardo Charbon, Fabio Sebastiano
This article presents a low-jitter and low-spur charge-sampling phase-locked loop (CSPLL). A charge-domain sub-sampling phase detector is introduced to achieve a high phase-detection gain and to reduce the PLL in-band phase noise. Even without employing an ...
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2021Reference Oversampling PLL Achieving −256-dB FoM and −78-dBc Reference Spur
This article presents a low jitter, low power, low reference spur LC oscillator-based reference oversampling digital phase locked loop (OSPLL). The proposed reference oversampling architecture simultaneously offers a low in-band phase noise, a wide-bandwid ...
IEEE2021A 10-to-12 GHz 5mW Charge-Sampling PLL Achieving 50 fsec RMS Jitter,-258.9 dB FOM and-65 dBc Reference Spur
Edoardo Charbon, Fabio Sebastiano
This paper presents a charge-sampling PLL (CSPLL), that demonstrates the best reported jitter-power FOM of -258.9 dB thanks to its high phase-detection gain and to the removal of the power-hungry buffer driving the phase detector. It also achieves -65 dBc ...
IEEE2020