Publications related to Diode–transistor logic

Inexact-Aware Architecture Design for Ultra-Low Power Bio-Signal Analysis

David Atienza Alonso, Giovanni Ansaloni, Pablo Garcia del Valle, Soumya Subhra Basu

This paper introduces an inexact, but ultra-low power, computing architecture devoted to the embedded analysis of bio-signals. The platform operates at extremely low voltage supply levels to minimize energy consumption. In this scenario, the reliability of ...

Inst Engineering Technology-Iet2016

Polarity control in WSe2 double-gate transistors

Giovanni De Micheli, Giovanni Vincenzo Resta, Pierre-Emmanuel Julien Marc Gaillardon

As scaling of conventional silicon-based electronics is reaching its ultimate limit, considerable effort has been devoted to find new materials and new device concepts that could ultimately outperform standard silicon transistors. In this perspective two-d ...

Nature Publishing Group2016

Inversion optimization in majority-inverter graphs

Giovanni De Micheli, Mathias Soeken, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù, Eleonora Testa, Odysseas Zografos

Many emerging nanotechnologies realize majority gates as primitive building blocks and they benefit from a majority-based synthesis. Recently, Majority-Inverter Graphs (MIGs) have been introduced to abstract these new technologies. We present optimi ...

Ieee2016

Fast Hierarchical NPN Classification

Giovanni De Micheli, Paolo Ienne, Mathias Soeken, Ana Petkovska

Classifying functions according to some common properties into libraries of functions is an important step in many logic synthesis and technology mapping algorithms used in FPGA design flows. NPN classification is one of the frequently used classifications ...

IEEE2016

Synthesis, Morphological, and Electro-optical Characterizations of Metal/Semiconductor Nanowire Heterostructures

Anna Fontcuberta i Morral, Sonia Conesa Boj, Heidi Andrea Potts

In this letter, we demonstrate the formation of unique Ga/GaAs/Si nanowire heterostructures, which were successfully implemented in nanoscale light-emitting devices with visible room temperature electroluminescence. Based on our recent approach for the int ...

American Chemical Society2016

Exploiting Circuit Duality to Speed Up SAT

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù, Maciej Jerzy Ciesielski

In this paper, we establish a non-trivial duality between tautology and contradiction check to speed up circuit SAT. Tautology check determines if a logic circuit is true in every possible interpretation. Analogously, contradiction check dete ...

IEEE2015

Modeling Minority Carriers Related Capacitive Effects for Transient Substrate Currents in Smart Power ICs

Maher Kayal, Jean-Michel Sallese, Camillo Stefanucci, Pietro Buccella

This paper presents an extended model for transient and ac circuit-level simulation of minority carriers propagation through the substrate of smart power integrated circuits (ICs). A p-n junction and a diffusion resistor with capacitive components are prop ...

Institute of Electrical and Electronics Engineers2015

Modeling Parasitic Vertical PNP in HVCMOS

Maher Kayal, Jean-Michel Sallese, Camillo Stefanucci, Pietro Buccella

High voltage CMOS active devices inherently have a parasitic vertical bipolar transistor. The parasitic PNP structure can be activated during high-power switching operation causing a potential shift of the substrate. In this work a spice-modeling approach ...

IEEE2015

A charge carrier transport model for donor-acceptor blend layers

Wolfgang Richard Tress

Highly efficient organic solar cells typically comprise donor-acceptor blend layers facilitating effective splitting of excitons. However, the charge carrier mobility in the blends can be substantially smaller than in neat materials, hampering the device p ...

American Institute of Physics2015

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Diode–transistor logic

Inexact-Aware Architecture Design for Ultra-Low Power Bio-Signal Analysis

Polarity control in WSe2 double-gate transistors

Inversion optimization in majority-inverter graphs

Fast Hierarchical NPN Classification

Synthesis, Morphological, and Electro-optical Characterizations of Metal/Semiconductor Nanowire Heterostructures

Exploiting Circuit Duality to Speed Up SAT

Polarity Control at Runtime

Modeling Minority Carriers Related Capacitive Effects for Transient Substrate Currents in Smart Power ICs

Modeling Parasitic Vertical PNP in HVCMOS

A charge carrier transport model for donor-acceptor blend layers

Graph Chatbot

Chat with Graph Search

Fast Hierarchical NPN Classification

Synthesis, Morphological, and Electro-optical Characterizations of Metal/Semiconductor Nanowire Heterostructures

A charge carrier transport model for donor-acceptor blend layers

Exploiting Circuit Duality to Speed Up SAT

Inversion optimization in majority-inverter graphs

Inexact-Aware Architecture Design for Ultra-Low Power Bio-Signal Analysis

Polarity control in WSe2 double-gate transistors

Modeling Minority Carriers Related Capacitive Effects for Transient Substrate Currents in Smart Power ICs

Polarity Control at Runtime

Modeling Parasitic Vertical PNP in HVCMOS