Publications related to Circuit underutilization

Active wire fences for multitenant FPGAs

Mirjana Stojilovic, Ognjen Glamocanin, Andela Kostic, Stasa Kostic

When spatially shared among multiple tenants, field-programmable gate arrays (FPGAs) are vulnerable to remote power side-channel analysis attacks. Using carefully crafted on-chip voltage sensors, adversaries can extract secrets (e.g., encryption keys or th ...

2023

Practical Implementations of Remote Power Side-Channel and Fault-Injection Attacks on Multitenant FPGAs

Francesco Regazzoni, Mirjana Stojilovic, Dina Gamaleldin Ahmed Shawky Mahmoud, Ognjen Glamocanin

Cloud computing environments increasingly provision FPGAs because of their fine-grained, highly parallel, and flexible hardware architecture. The availability of FPGAs in the cloud fueled research on the security risks associated with exposing FPGA fabric ...

Springer, Cham2023

Learning With Your PETS

Drazen Dujic, Andrea Cervone, Jules Christian Georges Macé, Max Dupont, Renan Pillon Barcelos

Recently, we published an article [1] presenting how the Power Electronics course at the bachelor level is organized by the Power Electronics Laboratory and taught at Ecole Polytechnique Fédérale de Lausanne, EPFL, Switzerland. For those avid readers who m ...

2023

A Visionary Look at the Security of Reconfigurable Cloud Computing

Francesco Regazzoni, Mirjana Stojilovic

Field-programmable gate arrays (FPGAs) have become critical components in many cloud computing platforms. These devices possess the fine-grained parallelism and specialization needed to accelerate applications ranging from machine learning to networking an ...

2023

A 500 x 500 Dual-Gate SPAD Imager With 100% Temporal Aperture and 1 ns Minimum Gate Length for FLIM and Phasor Imaging Applications

Edoardo Charbon, Claudio Bruschini, Andrei Ardelean, Paul Mos, Arin Can Ülkü, Michael Alan Wayne

In this article, we report on SwissSPAD3 (SS3), a 500 x 500 pixel single-photon avalanche diode (SPAD) array, fabricated in 0.18-mu m CMOS technology. In this sensor, we introduce a novel dual-gate architecture with two contiguous temporal windows, or gate ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Assessment of the Bundle SNSPD Plus FPGA-Based TDC for High-Performance Time Measurements

Christophe Marcel Georges Galland, Andrea Costa

Counting single photons and measuring their arrival time is of crucial importance for imaging and quantum applications that use single photons to outperform classical techniques. The investigation of the coincidence, i.e. correlation, between photons can b ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

FPGA Architecture: Principles and Progression

Paolo Ienne, Andrea Guerrieri, Lana Josipovic

Since their inception more than thirty years ago, field-programmable gate arrays (FPGAs) have been widely used to implement a myriad of applications from different domains. As a result of their low-level hardware reconfigurability, FPGAs have much faster d ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2021

Certification of the efficient random number generation technique based on single-photon detector arrays and time-to-digital converters

Edoardo Charbon, Samuel Burri

True random number generators (TRNGs) allow the generation of true random bit sequences, guaranteeing the unpredictability and perfect balancing of the generated values. TRNGs can be realised from the sampling of quantum phenomena, for instance, the detect ...

Hoboken2021

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Circuit underutilization

Active wire fences for multitenant FPGAs

Practical Implementations of Remote Power Side-Channel and Fault-Injection Attacks on Multitenant FPGAs

Learning With Your PETS

Evaluating, Exploiting, and Hiding Power Side-Channel Leakage of Remote FPGAs

A Visionary Look at the Security of Reconfigurable Cloud Computing

Automating the Design of Programmable Interconnect for Reconfigurable Architectures

A 500 x 500 Dual-Gate SPAD Imager With 100% Temporal Aperture and 1 ns Minimum Gate Length for FLIM and Phasor Imaging Applications

Assessment of the Bundle SNSPD Plus FPGA-Based TDC for High-Performance Time Measurements

FPGA Architecture: Principles and Progression

Certification of the efficient random number generation technique based on single-photon detector arrays and time-to-digital converters

Graph Chatbot

Chat with Graph Search

A Visionary Look at the Security of Reconfigurable Cloud Computing

Evaluating, Exploiting, and Hiding Power Side-Channel Leakage of Remote FPGAs

Learning With Your PETS

Assessment of the Bundle SNSPD Plus FPGA-Based TDC for High-Performance Time Measurements

Automating the Design of Programmable Interconnect for Reconfigurable Architectures

Active wire fences for multitenant FPGAs

Practical Implementations of Remote Power Side-Channel and Fault-Injection Attacks on Multitenant FPGAs

A 500 x 500 Dual-Gate SPAD Imager With 100% Temporal Aperture and 1 ns Minimum Gate Length for FLIM and Phasor Imaging Applications

FPGA Architecture: Principles and Progression

Certification of the efficient random number generation technique based on single-photon detector arrays and time-to-digital converters