Bipolar junction transistor

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Strain relaxation and multidentate anchoring in n-type perovskite transistors and logic circuits

Mohammad Khaja Nazeeruddin, Olga Syzgantseva

The engineering of tin halide perovskites has led to the development of p-type transistors with field-effect mobilities of over 70 cm2 V-1 s-1. However, due to their background hole doping, these perovskites are not suitable for n-type transistors. Ambipol ...

Nature Portfolio2024

Active Voltage Balancing with Seamless Integration into Dual Gate Driver for Series Connection of SiC MOSFETs

Drazen Dujic

The versatility of half-bridge configuration of silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) power module contributes to its widespread adoption, highlighting the popularity and significance of its corresponding dual gat ...

2024

Doping Engineering for PDP Optimization in SPADs Implemented in 55-nm BCD Process

Edoardo Charbon, Claudio Bruschini, Myung Jae Lee, Feng Liu

We introduce a new family of single-photon avalanche diodes (SPADs) with enhanced depletion regions in a 55-nm Bipolar-CMOS-DMOS (BCD) technology. We demonstrate how to systematically engineer doping profiles in the main junction and in deep p-well layers ...

Ieee-Inst Electrical Electronics Engineers Inc2024

A 73% Peak PDP Single-Photon Avalanche Diode Implemented in 110 nm CIS Technology With Doping Compensation

Edoardo Charbon, Claudio Bruschini, Ekin Kizilkan, Utku Karaca, Myung Jae Lee

In this article, we present 10 mu m diameter SPADs fabricated in 110 nm CIS technology based on an N (+) /HVPW junction, with enhanced sensitivity at short wavelengths. To reduce tunneling noise due to the highly-doped layers in the process, a doping compe ...

Ieee-Inst Electrical Electronics Engineers Inc2024

SPAD Developed in 55 nm Bipolar-CMOS-DMOS Technology Achieving Near 90% Peak PDP

Edoardo Charbon, Claudio Bruschini, Ekin Kizilkan, Pouyan Keshavarzian, Francesco Gramuglia, Won Yong Ha, Myung Jae Lee

We present a single-photon avalanche diode (SPAD) developed in 55 nm bipolar-CMOS-DMOS (BCD) technology, which achieves high photon detection probability (PDP) while its breakdown voltage is lower than 20 V. To enhance the PDP performance, the SPAD junctio ...

Ieee-Inst Electrical Electronics Engineers Inc2024

Towards Scalable Electronics: Synthetic 2D Materials for Large-Area 2D Circuit Integration

Zhenyu Wang

In the past decades, a significant increase of the transistor density on a chip has led to exponential growth in computational power driven by Moore's law. To overcome the bottleneck of traditional von-Neumann architecture in computational efficiency, effo ...

EPFL2024

Plasmoid drift and first wall heat deposition during ITER H-mode dual-SPIs in JOREK simulations

Mengdi Kong

The heat flux mitigation during the thermal quench (TQ) by the shattered pellet injection (SPI) is one of the major elements of disruption mitigation strategy for ITER. It's efficiency greatly depends on the SPI and the target plasma parameters, and is ult ...

IOP Publishing Ltd2024

Font Side Solutions for c-Si Solar Cells with High-Temperature Passivating Contacts

Ezgi Genç

In this work, we studied the potential of using thin films deposited by plasma-enhanced chemical vapor deposition (PECVD) for two main purposes: introducing an n-type passivating contact at the front of a TOPCon solar cell, or simplifying the fabrication o ...

EPFL2024

Investigation of room-temperature single-photon emitters in GaN-based materials and GaN/AlN quantum dots

Johann Nicolaï Stachurski

Over the past decade, quantum photonics platforms aiming at harnessing the fundamental properties of single particles, such as quantum superposition and quantum entanglement, have flourished. In this context, single-photon emitters capable of operating at ...

EPFL2024

Time-resolved multi-gate ion sensitive field effect transducer and system and method of operating the same

Jean-Michel Sallese, Adil Koukab

A time-resolved multi-gate ion sensitive field effect transducer, including a silicon layer, a P-doped region in the silicon layer and a first electrode in electric connection with the P doped region, a N-doped region in the silicon layer and a second elec ...

2023

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