Altera | EPFL Graph Search

Altera Corporation was a manufacturer of programmable logic devices (PLDs) headquartered in San Jose, California. It was founded in 1983 and acquired by Intel in 2015. The main product lines from Altera were the flagship Stratix series, mid-range Arria series, and lower-cost Cyclone series system on a chip field-programmable gate arrays (FPGAs); the MAX series complex programmable logic device and non-volatile FPGAs; Quartus design software; and Enpirion PowerSoC DC-DC power solutions. The company was founded in 1983 by semiconductor veterans Rodney Smith, Robert Hartmann, James Sansbury, and Paul Newhagen with

500,000 in seed money. The name of the company was a play on "alterable", the type of chips the company created. In 1984, the company formed a long-running design partnership with Intel, and 1988, became a public company via an initial public offering. In 1994, Altera acquired the PLD business of Intel for

50 million. On December 28, 2015, the company was acquired by Intel. The Stratix series FPGAs were the company's largest, highest bandwidth devices, with up to 1.1 million logic elements, integrated transceivers at up to 28 Gbit/s, up to 1.6 Tbit/s of serial switching capability, up to 1,840 GMACs of signal-processing performance, and up to 7 x72 DDR3 memory interfaces at 800 MHz. In September 2000, the company acquired Northwest Logic to expand its design services for delivery of complete system-on-chip solutions. In May 2013, Altera made available SDK for OpenCL, enabling software programmers to access the high-performance capabilities of programmable logic devices. Beginning in December 2012, the company produced system on a chip FPGA devices using a fully depleted silicon on insulator (FDSOI) chip manufacturing process. These devices integrated FPGAs with full hard processor systems based around ARM architecture onto a single device. In May 2013, Altera acquired embedded power chipmaker Enpirion for approximately $140 million in cash, providing Altera with power system on a chip DC-DC converters that enabled greater power densities and lower noise performance compared with their discrete equivalent.

Pyramic array: An FPGA based platform for multi-channel audio acquisition

Juan Azcarreta Ortiz

Microphone arrays techniques present compelling applications for robotic applications. Those techniques can allow robots to listen to their environment and infer clues from it. Such features might enable capabilities such as natural interaction with humans, interpreting spoken commands or the localization of victims during search and rescue tasks. However, under noisy conditions robotic implementations of microphone arrays might degrade their precision when localizing sound sources. For practical applications, human hearing still leaves behind microphone arrays. Daniel Kisch is an example of how humans are able to efficiently perform echo-localization to recognize their environment, even in noisy and reverberant environments. For ubiquitous computing, another limitation of acoustic localization algorithms is within their capabilities of performing real-time Digital Signal Processing (DSP) operations. To tackle those problems, tradeoffs between size, weight, cost and power consumption compromise the design of acoustic sensors for practical applications. This works presents the design and operation of a large microphone array for DSP applications in realistic environments. To address those problems this project introduces the Pyramic sound capture system designed at LAP in EPFL. Pyramic is a custom hardware which possesses 48 microphones distributed in the edges of a tetrahedron. The microphone arrays interact with a Terasic DE1-SoC board from Altera Cyclone V family devices, which combines a Hard Processor System (HPS) and a Field Programmable Gate Array (FPGA) in the same die. The HPS part integrates a dual-core ARM-based Cortex-A9 processor, which combined with the power of FPGA design suitable for processing multichannel microphone signals. This thesis explains the implementation of the Pyramic array. Moreover, FPGA-based hardware accelerators have been designed to implement a Master SPI communication with the array and a parallel 48 channels FIR filters cascade of the audio data for delay-and-sum beamforming applications. Additionally, the configuration of the HPS part allows the Pyramic array to be controlled through a Linux based OS. The main purpose of the project is to develop a flexible platform in which real-time echo-location algorithms can be implemented. The effectiveness of the Pyramic array design is illustrated by testing the recorded data with offline direction of arrival algorithms developed at LCAV in EPFL.

2016

Pyramic array: An FPGA based platform for multi-channel audio acquisition

Juan Azcarreta Ortiz

2016