Publications related to Logic level

Thermo-optic epsilon-near-zero effects

Camille Sophie Brès, Marco Clementi, Jiaye Wu, Qian Li

Nonlinear epsilon-near-zero (ENZ) nanodevices featuring vanishing permittivity and CMOS-compatibility are attractive solutions for large-scale-integrated systems-on-chips. Such confined systems with unavoidable heat generation impose critical challenges fo ...

Berlin2024

A Delay and Power Efficient Voltage Level Shifter with Low Leakage Power

Alexandre Schmid, Mehdi Saberi

This paper presents a new power-efficient and high-speed voltage level shifter. In the proposed structure, the existing contentions at the internal nodes are reduced using auxiliary transistors and feedback networks, leading to a significant reduction in t ...

New York2023

Towards Single Photon Detection with Amorphous Silicon Based Microchannel Plates

Janina Christine Isabelle Löffler

An exciting new approach for microchannel plate (MCP) detectors could help make them suitable for single photon detection. State-of-the-art clean room technology allows amorphous silicon based microchannel plates (AMCPs) to take a variety of shapes. This v ...

EPFL2021

A hybrid III-V tunnel FET and MOSFET technology platform integrated on silicon

Mihai Adrian Ionescu, Kirsten Emilie Moselund, Clarissa Convertino

InGaAs/GaAsSb tunnelling field-effect transistors and InGaAs metal-oxide-semiconductor field-effect transistors can be integrated on the same silicon substrate using conventional CMOS-compatible processes, creating a platform for potential use in low-power ...

NATURE RESEARCH2021

Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic

Giovanni De Micheli, Mathias Soeken, Eleonora Testa, Odysseas Zografos

Emerging technologies such as plasmonics and photonics are promising alternatives to CMOS for high throughput applications, thanks to their waveguide's low power consumption and high speed of computation. Besides these qualities, these novel technologies a ...

2020

Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic

Giovanni De Micheli, Mathias Soeken, Eleonora Testa, Odysseas Zografos

Emerging technologies such as plasmonics and photonics are promising alternatives to CMOS for high throughput applications, thanks to their waveguide's low power consumption and high speed of computation. Besides these qualities, these novel technologies a ...

IEEE2020

Intrinsic or nucleation-driven switching: An insight from nanoscopic analysis of negative capacitance Hf1-xZrxO2-based structures

Mihai Adrian Ionescu, Igor Stolichnov, Matteo Cavalieri, Carlotta Gastaldi

HfO2-based ferroelectrics have dramatically changed the application perspectives of polarization-switching materials for information processing and storage. Their CMOS compatibility and preservation of high reversible polarization down to a few nanometer t ...

AMER INST PHYSICS2020

Physical Model of Low-Temperature to Cryogenic Threshold Voltage in MOSFETs

Christian Enz, Farzan Jazaeri, Arnout Lodewijk M Beckers

This article presents a physical model of the threshold voltage in MOSFETs valid down to 4.2 K. Interface traps close to the band edge modify the saturating temperature behavior of the threshold voltage observed in cryogenic measurements. Dopant freezeout, ...

2020

RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM

Alexandre Sébastien Julien Levisse

Resistive RAM (RRAM) is a promising emerging Non-Volatile Memory candidate due to its scalability and CMOS compatibility, which enables the fabrication of high density RRAM crossbar arrays in Back-End-Of-Line CMOS processes. Fast and accurate architectural ...

2019

RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM

Alexandre Sébastien Julien Levisse

Resistive RAM (RRAM) is a promising emerging Non-Volatile Memory candidate due to its scalability and CMOS compatibility, which enables the fabrication of high density RRAM crossbar arrays in Back-End-Of-Line CMOS processes. Fast and accurate architectural ...

2019

Logic level

Thermo-optic epsilon-near-zero effects

A Delay and Power Efficient Voltage Level Shifter with Low Leakage Power

Towards Single Photon Detection with Amorphous Silicon Based Microchannel Plates

A hybrid III-V tunnel FET and MOSFET technology platform integrated on silicon

Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic

Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic

Intrinsic or nucleation-driven switching: An insight from nanoscopic analysis of negative capacitance Hf1-xZrxO2-based structures

Physical Model of Low-Temperature to Cryogenic Threshold Voltage in MOSFETs

RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM

RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM

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Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic

Towards Single Photon Detection with Amorphous Silicon Based Microchannel Plates

Intrinsic or nucleation-driven switching: An insight from nanoscopic analysis of negative capacitance Hf1-xZrxO2-based structures

RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM

A hybrid III-V tunnel FET and MOSFET technology platform integrated on silicon

Physical Model of Low-Temperature to Cryogenic Threshold Voltage in MOSFETs

RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM

Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic