Verilog

Summary

Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction. It is also used in the verification of analog circuits and mixed-signal circuits, as well as in the design of genetic circuits. In 2009, the Verilog standard (IEEE 1364-2005) was merged into the SystemVerilog standard, creating IEEE Standard 1800-2009. Since then, Verilog is officially part of the SystemVerilog language. The current version is IEEE standard 1800-2017. Overview Hardware description languages such as Verilog are similar to software programming languages because they include ways of describing the propagation time and signal strengths (sensitivity). There are two types of assignment operators; a blocking assignment (=), and a non-blocking (

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https://en.wikipedia.org/wiki/Verilog

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Physics-based compact model for ultra-scaled FinFETs

Christophe Lallement, Jean-Michel Sallese, Ashkhen Yesayan

A physical and explicit compact model for lightly doped FinFETs is presented. This design-oriented model is valid for a large range of silicon Fin widths and lengths, using only a very few number of model parameters. The quantum mechanical effects (QMEs), which are very significant for thin Fins below 15 nm, are included in the model as a correction to the surface potential. A physics-based approach is also followed to model short-channel effects (roll-off), drain-induced barrier lowering (DIBL), subthreshold slope degradation, drain saturation voltage, velocity saturation, channel length modulation and carrier mobility degradation. The quasi-static model is then developed and accurately accounts for small-geometry effects as well. This compact model is accurate in all regions of operation, from weak to strong inversion and from linear to saturation regions. It has been implemented in the high-level language Verilog-A and exhibits an excellent numerical efficiency. Finally, comparisons of the model with 3D numerical simulations show a very good agreement making this model well-suited for advanced circuit simulations. (C) 2011 Elsevier Ltd. All rights reserved.

2011

Analytic modelling of passive microfluidic mixers

Christophe Lallement, Jean-Michel Sallese

This paper deals with a new analytical model for microfluidic passive mixers. Two common approaches already exist for such a purpose. On the one hand, the resolution of the advection-diffusion-reaction equation (ADRE) is the first one and the closest to physics. However, ADRE is a partial differential equation that requires finite element simulations. On the other hand, analytical models based on the analogy between microfluidics and electronics have already been established. However, they rely on the assumption of homogeneous fluids, which means that the mixer is supposed to be long enough to obtain a perfect mixture at the output. In this paper, we derive an analytical model from the ADRE under several assumptions. Then we integrate these equations within the electronic-equivalent models. The resulting models computed the relationship between pressure and flow rate in the microfluidic circuit but also takes the concentration gradients that can appear in the direction perpendicular to the channel into account. The model is compared with the finite element simulation performed with COMSOL Multiphysics in several study cases. We estimate that the global error introduced by our model compared to the finite element simulation is less than 5% in every use case. In counterparts, the cost in terms of computational resources is drastically reduced. The analytical model can be implemented in a large range of modelling and simulation languages, including SPICE and hardware description language such as Verilog-AMS. This feature is very interesting in the context of the in silico prototyping of large-scale microfluidic devices or multi-physics devices involving microfluidic circuits, e.g. lab-on-chips.

AMER INST MATHEMATICAL SCIENCES-AIMS2022

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In this paper, we developed a simulation-based architecture evaluation framework for field-programmable gate arrays (FPGAs), called FPGA-SPICE, which enables automatic layout-level estimation and electrical simulations of FPGA architectures. FPGA-SPICE can automatically generate Verilog and SPICE netlists based on realistic FPGA configurations and a high-level eTtensible Markup Language-based FPGA architectural description language. The outputted Verilog netlists can be used to generate layouts of full FPGA fabrics through a semicustom design flow. SPICE simulation decks can be generated at three levels of complexity, namely, full-chip-level, grid-level, and component-level, providing different tradeoff between accuracy and simulation time. In order to enable such level of analysis, we presented two SPICE netlist partitioning techniques: loads extraction and parasitic net activity estimation. Electrical simulations showed that averaged over the selected benchmarks, the grid-/component-level approach can achieve 6.1x/7.5x execution speed-up with 9.9%/8.3% accuracy loss, respectively, compared to the full-chip level simulation. FPGA-SPICE was showcased through three different case studies: 1) an area breakdown analysis for static random access memory-based FPGAs, showing that configuration memories are a dominant factor; 2) a power breakdown comparison to analytical models, analyzing the source of accuracy loss; and 3) a robustness evaluation against process corners, studying their impact on energy consumption of full FPGA fabrics.

2018