Static random-access memory

Summary

Static random-access memory (static RAM or SRAM) is a type of random-access memory (RAM) that uses latching circuitry (flip-flop) to store each bit. SRAM is volatile memory; data is lost when power is removed. The term static differentiates SRAM from DRAM (dynamic random-access memory) — SRAM will hold its data permanently in the presence of power, while data in DRAM decays in seconds and thus must be periodically refreshed. SRAM is faster than DRAM but it is more expensive in terms of silicon area and cost; it is typically used for the cache and internal registers of a CPU while DRAM is used for a computer's main memory. History Semiconductor bipolar SRAM was invented in 1963 by Robert Norman at Fairchild Semiconductor. MOS SRAM was invented in 1964 by John Schmidt at Fairchild Semiconductor. It was a 64-bit MOS p-channel SRAM. The SRAM was the main driver behind any new CMOS-based technology fabrication process since 1959 when CMOS was invented. In 1964, Arnold Far

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Replica Bit-Line Technique for Internal Refresh in Logic-Compatible Gain-Cell Embedded DRAM

Robert Giterman, Odem Harel

Embedded memories, mostly implemented with static random access memory (SRAM), dominate the area and power of integrated circuits. Gain-cell embedded DRAM (GC-eDRAM) is an alternative to SRAM due to its high density, low power consumption, and two-ported functionality. However, GC-eDRAM requires periodic refresh cycles to maintain its data due to its dynamic storage mechanism. The refresh operation is typically handled at a memory controller level, resulting in an energy overhead and limited memory availability. In this paper, we propose a new approach for the realization of the refresh operation using an internal refresh mechanism, which supports an efficient row-wise refresh operation within a single clock cycle, providing 100% write access availability at a reduced refresh latency and power. An 8 kbit GC-eDRAM array with integrated internal refresh and replica bit-line was implemented, demonstrating up-to 30% reduced refresh latency and 65% reduced read energy at a low cost of 2.4% array area overhead, compared to a conventional GC-eDRAM array without internal refresh capabilities.

ELSEVIER SCI LTD2020

Variability-Aware Design Space Exploration of Embedded Memories

Andreas Peter Burg, Shrikanth Ganapathy, Georgios Karakonstantis

With scaling of process technologies and worsening of process variations, embedded memories are susceptible to a large number of failure mechanisms making it hard to achieve high yield. In this paper, by bringing together architecture and circuit-level exploration tools, we analyse the impact of process variations on static random access memory (SRAM) cell stability and determine the impact of SRAM failures on memory functional yield. We then detail the importance of repair mechanisms such as error correcting codes (ECC) and redundancy on improving yield subject to constraints set on power and area. Finally, we show that a design paradigm orthogonal to traditional repair mechanisms involving redefinition of the yield criterion by accepting memories with failures is a promising candidate for improving yield without incurring additional overheads.

2014

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Computing servers play a key role in the development and process of emerging compute-intensive applications in recent years. However, they need to operate efficiently from an energy perspective viewpoint, while maximizing the performance and lifetime of the hottest server components (i.e., cores and cache). Previous methods focused on either improving energy efficiency by adopting new hybrid-cache architectures including the resistive random-access memory (RRAM) and static random-access memory (SRAM) at the hardware level, or exploring trade-offs between lifetime limitation and performance of multi-core processors under stable workloads conditions. Therefore, no work has so far proposed a co-optimization method with hybrid-cache-based server architectures for real-life dynamic scenarios taking into account scalability, performance, lifetime reliability, and energy efficiency at the same time. In this paper, we first formulate a reliability model for the hybrid-cache architecture to enable precise lifetime reliability management and energy efficiency optimization. We also include the performance and energy overheads of cache switching, and optimize the benefits of hybrid-cache usage for better energy efficiency and performance. Then, we propose a runtime Q-Learning-based reliability management and performance optimization approach for multi-core microprocessors with the hybrid-cache architecture, jointly incorporated with a dynamic preemptive priority queue management method to improve the overall tasks' performance by targeting to respect their end time limits. Experimental results show that our proposed method achieves up to 44% average performance (i.e., tasks execution time) improvement, while maintaining the whole system design lifetime longer than 5 years, when compared to the latest state-of-the-art energy efficiency optimization and reliability management methods for computing servers.

2022