Complex instruction set computer

Related publications (15)

Surveillance continue des transformateurs de puissance par réseaux de neurones auto-organisés

An outage of a power transformer, generally, has heavy financial consequences for electric power systems utilities. In order to prevent any failure and to optimize their maintenance, a growing number of operating parameters are measured on-line. The important amount of data together with the ever increasing number of units to be monitored calls for automatic alarm devices. Due to the complexity of power transformers, the evolution of the operating parameters is hardly known and, in fact, difficult to model. That is why the alarms, generally, start on thresholds defined independently for each recorded variable. With such an approach, neither variations in relation to operating conditions, nor existing relations between different monitored quantities are taken into consideration. This thesis is devoted to the study of an "intelligent" on-line monitoring system, able to adapt itself depending on those variations. The developed solution uses self-organizing maps (SOM). It consists of unsupervised neural networks inspired by the organization of cortical zones in the brains of mammals. Their characteristics enable them to represent a complex set of data in a generally dimensional space preserving at the same time, the topology of the original set as truthfully as possible. This work shows, more specifically, that these systems allow to model the different states of a transformer preserving not only the general structure of data, but also their local correlations. The topological preservation feature of the maps implies that close operating states will also be close on the map. Based on this observation, a powerful graphic interface is proposed to exploit qualitatively the measurement results. The monitoring is considered in the real context for which, in case of a defect, the transformer behaviour is generally unknown. This constraint resulted in the study of the self-organizing map response for states located outside the original model space. A confidence indicator quantifying the accuracy of the model response was proposed. It is shown that this indicator allows to define an adaptive alarm threshold that complements the developed tool for qualitative interpretation. The developed approach is finally validated using data collected on a pilot-transformer, operating in the Swiss electric network. The obtained results show the pertinence of the proposed technique and its ability to reveal any sudden change of one or several variables with a relatively sharp sensitivity.

EPFL2001

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Linebacker: Preserving Victim Cache Lines in Idle Register Files of GPUs

Yunho Oh

Modern GPUs suffer from cache contention due to the limited cache size that is shared across tens of concurrently running warps. To increase the per-warp cache size prior techniques proposed warp throttling which limits the number of active warps. Warp throttling leaves several registers to be dynamically unused whenever a warp is throttled. Given the stringent cache size limitation in GPUs this work proposes a new cache management technique named Linebacker (LB) that improves GPU performance by utilizing idle register file space as victim cache space. Whenever a CTA becomes inactive, linebacker backs up the registers of the throttled CTA to the off-chip memory. Then, linebacker utilizes the corresponding register file space as victim cache space. If any load instruction finds data in the victim cache line, the data is directly copied to the destination register through a simple register-register move operation. To further improve the efficiency of victim cache linebacker allocates victim cache space only to a select few load instructions that exhibit high data locality. Through a careful design of victim cache indexing and management scheme linebacker provides 29.0% of speedup compared to the previously proposed warp throttling techniques.

ASSOC COMPUTING MACHINERY2019

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Full System Exploration of On-Chip Wireless Communication on Many-Core Architectures

Giovanni Ansaloni, David Atienza Alonso, Joshua Alexander Harrison Klein, Rafael Medina Morillas, Yasir Mahmood Qureshi, Marina Zapater Sancho

In order to develop sustainable and more powerful information technology (IT) infrastructures, the challenges posed by the "memory wall" are critical for the design of high-performance and high-efficiency many-core computing systems. In this context, recent advances in the integration of nano-antennas, enabling novel short-distance communication paradigms, promise disruptive gains. To gauge their potential benefit for the next-generation of many-core server designs, it is crucial to explore the impact of wireless communication links from a whole-system viewpoint, considering complex architectures and applications characteristics. To this end, in this work we introduce an extension to the popular gem5 full system-level simulator, enabling the simulation of many-core platforms featuring on-chip wireless channels. This new extension allows the flexible investigation of different combinations of wireless and wired interconnects, as well as diverse connection protocols. We showcase its capabilities by performing an architectural exploration, targeting a multi-core system executing image inference using an AlexNet Neural Network benchmark. A 2.3x speedup is obtained when implementing wireless communication between cores instead of traditional on-chip wired interconnects.

2022

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Related concepts (37)

Reduced instruction set computer

In computer engineering, a reduced instruction set computer (RISC) is a computer architecture designed to simplify the individual instructions given to the computer to accomplish tasks. Compared to

Microprocessor

A microprocessor is a computer processor where the data processing logic and control is included on a single integrated circuit (IC), or a small number of ICs. The microprocessor contains the ar

X86

x86 (also known as 80x86 or the 8086 family) is a family of complex instruction set computer (CISC) instruction set architectures initially developed by Intel based on the Intel 8086 microprocesso

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Multiprocessors are a core component in all types of computing infrastructure, from phones to datacenters. This course will build on the prerequisites of processor design and concurrency to introduce the essential technologies required to combine multiple processing elements into a single computer.

The course introduces the students to the basic notions of computer architecture and, in particular, to the choices of the Instruction Set Architecture and to the memory hierarchy of modern systems.

Microcontrôleurs et conception de systèmes numériques couvre le fonctionnement interne d'un microcontrôleur, des notions de base d'architecture de processeur et de système informatique ainsi que les interfaces de microcontrôleurs, et protocoles de communication série.

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Related lectures (4)

Lecture 11 - GPUs 2 (2020)

CS-307: Introduction to multiprocessor architecture

MCU-L03

EE-208: Microcontrollers and digital systems

EE-556 / Lecture 7 - 1/2 (2020)

EE-556: Mathematics of data: from theory to computation