Covers layout optimization techniques for CMOS circuit design, including common-centroid layout, MOSFET sizing, gain simulation, and performance analysis.
Explores the implementation of logic gates in semiconductor material, focusing on TTL and CMOS technologies, ICs, hazards, clocks, D flip-flops, and switch debouncing.
Provides an overview of the technology behind logic gates, covering TTL and CMOS families and addressing static and dynamic hazards, gated clocks, and switch debouncing.
Covers energy dissipation in VLSI chips, focusing on subthreshold current in NMOS transistors and the effects of threshold voltage on power consumption.
