Simulation-Based Verification

In course

Description

This lecture covers simulation-based verification in VLSI systems, focusing on compiled-code and event-driven algorithms. It explains the purpose of simulation, modeling levels, signal states, and the advantages and drawbacks of each algorithm. The instructor discusses levelization examples and the event-driven algorithm's efficiency for discrete-event simulations.

Instructor

Official source

https://mediaspace.epfl.ch/media/0_xuexfcu4

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Related lectures (3)

Related concepts (53)

Logic simulation

Logic simulation is the use of simulation software to predict the behavior of digital circuits and hardware description languages. Simulation can be performed at varying degrees of physical abstraction, such as at the transistor level, gate level, register-transfer level (RTL), electronic system-level (ESL), or behavioral level. Logic simulation may be used as part of the verification process in designing hardware. Simulations have the advantage of providing a familiar look and feel to the user in that it is constructed from the same language and symbols used in design.

Functional verification

Functional verification is the task of verifying that the logic design conforms to specification. Functional verification attempts to answer the question "Does this proposed design do what is intended?" This is complex and takes the majority of time and effort (up to 70% of design and development time) in most large electronic system design projects. Functional verification is a part of more encompassing design verification, which, besides functional verification, considers non-functional aspects like timing, layout and power.

Transaction-level modeling

Transaction-level modeling (TLM) is an approach to modelling complex digital systems by using electronic design automation software. TLM language (TLML) is a hardware description language, usually, written in C++ and based on SystemC library. TLMLs are used for modelling where details of communication among modules are separated from the details of the implementation of functional units or of the communication architecture. It's used for modelling of systems that involve complex data communication mechanisms.

High-level synthesis

High-level synthesis (HLS), sometimes referred to as C synthesis, electronic system-level (ESL) synthesis, algorithmic synthesis, or behavioral synthesis, is an automated design process that takes an abstract behavioral specification of a digital system and finds a register-transfer level structure that realizes the given behavior. Synthesis begins with a high-level specification of the problem, where behavior is generally decoupled from low-level circuit mechanics such as clock-level timing.

Discrete-event simulation

A discrete-event simulation (DES) models the operation of a system as a (discrete) sequence of events in time. Each event occurs at a particular instant in time and marks a change of state in the system. Between consecutive events, no change in the system is assumed to occur; thus the simulation time can directly jump to the occurrence time of the next event, which is called next-event time progression.