Publications by Didier Bouvet | EPFL Graph Search

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Design Space of Twin Gate Junctionless Vertical Slit Field Effect Transistors

Heavily Doped Junctionless Vertical Slit FETs with Slit Width Below 20 nm

Downscaling and Short Channel Effects in Twin Gate Junctionless Vertical Slit FETs

Gate-all-around buckled dual Si nanowire nMOSFETs on bulk Si for transport enhancement and digital logic

Accumulation-mode gate-all-around Si nanowire nMOSFETs with sub-5 nm cross-section and high uniaxial tensile strain

Multigate Buckled Self-Aligned Dual Si Nanowire MOSFETs on Bulk Si for High Electron Mobility

Uniaxially tensile strained accumulation-mode gate-all-around Si nanowire nMOSFETs

Modeling the Temperature Dependence of Fe-FET Static Characteristics Based on Landau's Theory

Accumulation-Mode GAA Si NW nFET with sub-5 nm cross-section and high uniaxial tensile strain

Influence of chelating agents on the tribocorrosion of tungsten in sulphuric acid solution